Analog Integrated Circuit Device Data



Freescale Semiconductor

28

BC3770

5.5.5

Control Register Map

5.5.5.1

INT1: Interrupt Register 1 for Abnormal Conditions

Address

(hex)

Register

Name

Reset

(hex)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00

INT1

00

VBUSOVP

VBUSUVLO

VBUSINOK

AICL

VBUSLIMIT

BATOVP

THEMSHDN

THEMREG

01

INT2

00

FASTTMROFF

NOBAT

WEAKBAT

OTGFAIL

PRETMROFF

CHGRSTF

DONE

TOPOFF

02

INT3

00

Reserved

Reserved

Reserved

Reserved

VSYSOK

VSYSNG

VSYSOLP

DISLIMIT

03

INTMSK1

03

VBUSOVPM

VBUSUVLOM

VBUSINOKM

AICLM

VBUSINLIMIT

M

BATOVPM

THEMSHDNM

THEMREGM

04

INTMSK2

B8

FASTTMROFF

M

NOBATM

WEAKBATM

OTGFAILM

PRETMROFF

M

CHGRSTFM

DONEM

TOPOFFM

05

INTMSK3

FF

Reserved

Reserved

Reserved

Reserved

VSYSOKM

VSYSNGM

VSYSOLPM

DISLIMITM

06

STATUS

N/A

Reserved

Reserved

Reserved

VSYSOLP

DISLIMIT

THEMSHDN

BATDET

SUSPEND

07

CTRL

42

Reserved

ENCOMPARA

TOR

Reserved

Reserved

RESET

SUSPEN

CHGEN

ENBOOST

08

VBUSCTRL

08

Reserved

Reserved

VBUSLIMIT

09

CHGCTRL1

2F

Reserved

AICLTH

AUTOSTOP

AICLEN

PRECHG

0A

CHGCTRL2

08

Reserved

Reserved

FASTCHG

0B

CHGCTRL3

4C

BATREG

WEAKBAT

0C

CHGCTRL4

05

Reserved

TOPOFF

DISLIMIT

0D

CHGCTRL5

0F

Reserved

Reserved

VOTG

FASTTIMER

TOPOFFTIMER

Address (hex)

Mode

Reset Condition:

VSYS

Reset: 0x00

00

R/C

Bit

Name

Reset

Description

7

VBUSOVP

0

1: VBUS OVP event detected

6

VBUSUVLO

0

1: VBUS falling UVLO detected

5

VBUSINOK

0

1: Valid VBUS detected

4

AICL

0

1: AICL threshold detected

3

VBUSLIMIT

0

1: VBUS input current limit detected

2

BATOVP (17), (18)

0

1: BAT OVP detected

1

THEMSHDN

0

1: Thermal shutdown detected

0

THEMREG

0

1: Thermal regulation threshold detected

Notes

17.

These interrupts are to be set to 1 when “ENCOMPARATOR” bit 7 in the 07h register set to “1” AND no valid VBUS supply is at preset. If

“ENCOMPARATOR” bit 7 is reset to “0” in no valid VBUS supply, these interrupt events are in no response.

18.

These interrupts are to be forcibly overridden to alert the interrupt events in a valid VBUS attached.