AD7768 datasheet(49/99 Pages) AD

49 / 99 page

Data Sheet

AD7768/AD7768-4

Rev. A | Page 49 of 99

Channel Standby

Table 21 and Table 23 show how the user can put channels into

standby mode. Set either ST0 or ST1 to Logic 1 to place banks of

four channels into standby mode. When in standby mode, the

channels are disabled but still hold their position in the output

data stream. The 8-bit header and 24-bit conversion result are

set to all zeros when the ADC channels are set to standby.

The VCM voltage output is associated with the Channel 0

circuitry. If Channel 0 is put into standby mode, the VCM

voltage output is also disabled for maximum power savings.

Channel 0 must be enabled while VCM is being used externally

to the AD7768/AD7768-4.

The crystal excitation circuitry is associated with the Channel 4

(Channel 2 on the AD7768-4) circuitry. If Channel 4 (Channel 2

on the AD7768-4) is put into standby mode, the crystal circuitry is

also disabled for maximum power savings. Channel 4 must be

enabled while the external crystal is used on the AD7768.

Channel 2 must be enabled while the external crystal is used on

the AD7768-4.

Table 21. Truth Table for the AD7768 ST0 and ST1 Pins

ST1

ST0

Function

All channels operational.

Channel 0 to Channel 3 in

standby. Channel 4 to

Channel 7 operational.

Channel 4 to Channel 7 in

standby. Channel 0 to

Channel 3 operational.

All channels in standby.

Table 22. Truth Table for the AD7768-4 ST0 Pin

ST0

Function

All channels operational.

Channel 0 to Channel 3 in standby.

SPI CONTROL

The AD7768/AD7768-4 have a 4-wire SPI interface that is

compatible with QSPI™, MICROWIRE®, and DSPs. The interface

operates in SPI Mode 0. In SPI Mode 0, SCLK idles low, the

falling edge of CS clocks out the MSB, the falling edge of SCLK

is the drive edge, and the rising edge of SCLK is the sample

edge. This means that data is clocked out on the falling/drive

edge and data is clocked in on the rising/sample edge.

DRIVE EDGE

SAMPLE EDGE

Figure 78. SPI Mode 0 SCLK Edges

Accessing the ADC Register Map

To use SPI control mode, set the PIN/SPI pin to logic high. The

SPI control operates as a 16-bit, 4-wire interface, allowing read

and write access. Figure 80 shows the interface format between

the AD7768/AD7768-4 and the digital host.

The SPI serial control interface of the AD7768 is an independent

path for controlling and monitoring the AD7768. There is no

direct link to the data interface. The timing of MCLK and

DCLK is not directly related to the timing of the SPI control

interface. However, the user must ensure that the SPI reads and

writes satisfy the minimum t30 specification (see Table 4 and

Table 6) so that the AD7768/AD7768-4 can detect changes to

the register map.

SPI access is ignored during the period immediately after a

reset. Allow the full ADC start-up time after reset (see Table 1)

to elapse before accessing the AD7768/AD7768-4 over the SPI

interface.

Table 23. MODEx Example Selection

Mode Hex

MODE3

MODE2

MODE1

MODE0

Power Mode

DCLK Frequency

Data Conversion

0x3

Eco

MCLK/8

Standard

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