AD7768 datasheet(74/99 Pages) AD

74 / 99 page

AD7768/AD7768-4

Data Sheet

Rev. A | Page 74 of 99

CHANNEL STANDBY REGISTER

Address: 0x00, Reset: 0x00, Name: Channel Standby

Each of the ADC channels can be put into standby mode independently by setting the appropriate bit in the channel standby register.

When a channel is in standby mode, its position in the data output stream is held. The 8-bit header is all zeros, as is the conversion result

output of 24 zeros.

The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also

disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7768.

The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby mode, the crystal circuitry is

also disabled for maximum power savings. Channel 4 must be enabled while the external crystal is used on the AD7768.

Table 38. Bit Descriptions for Channel Standby

Bits

Bit Name

Settings

Description

Reset

Access

CH_7

Channel 7

0x0

Enabled

Standby

CH_6

Channel 6

0x0

Enabled

Standby

CH_5

Channel 5

0x0

Enabled

Standby

CH_4

Channel 4

0x0

Enabled

Standby

CH_3

Channel 3

0x0

Enabled

Standby

CH_2

Channel 2

0x0

Enabled

Standby

CH_1

Channel 1

0x0

Enabled

Standby

CH_0

Channel 0

0x0

Enabled

Standby

CHANNEL MODE A REGISTER

Address: 0x01, Reset: 0x0D, Name: Channel Mode A

Two mode options are available on the AD7768 ADCs. The channel modes are defined by the contents of the Channel Mode A and

Channel Mode B registers. Each mode is then mapped as desired to the required ADC channel. Channel Mode A and Channel Mode B

allow different filter types and decimation rates to be selected and mapped to any of the ADC channels.

When different decimation rates are selected, the AD7768 output a data ready signal at the fastest selected decimation rate. Any channel

that runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero

and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output:

Header and Data section).

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