AD7768 datasheet(63/99 Pages) AD

63 / 99 page

Data Sheet

AD7768/AD7768-4

Rev. A | Page 63 of 99

Filter Type

In pin control mode, all channels operate using one filter

selection. The filter selected in pin control mode is determined

by the logic level of the FILTER pin. In SPI control mode, the

digital filters can be selected on a per channel basis, using the

mode registers. This header bit is 0 for channels using the

wideband filter, and 1 for channels using the sinc5 filter.

Filter Saturated

The filter saturated bit indicates that the filter output is clipping at

either positive or negative full scale. The digital filter clips if the

signal goes beyond the specification of the filter; it does not wrap.

The clipping may be caused by the analog input exceeding the

analog input range, or by a step change in the input, which may

cause overshoot in the digital filter. Clipping may also occur

when the combination of the analog input signal and the channel

gain register setting cause the signal seen by the filter to be

higher than the analog input range.

Channel ID

The channel ID bits indicate the ADC channel from which the

succeeding conversion data originates (see Table 34).

Table 34. Channel ID vs. Channel Number

Channel

Channel ID 2

Channel ID 1

Channel ID 0

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Data Interface: Standard Conversion Operation

In standard mode operation, the AD7768/AD7768-4 operate as

the master and stream data to the DSP or FPGA. The AD7768/

AD7768-4 supply the data, the data clock (DCLK), and a falling

edge framing signal (DRDY) to the slave device. All of these

signals are synchronous. The data interface connections to

DSP/FPGA are shown in Figure 102. The FORMATx pins

determine how the data is output from the AD7768/AD7768-4.

Figure 97 through Figure 99 show the data interface operating

in standard mode at the maximum data rate. In all instances,

DRDY is asserted one clock cycle before the MSB of the data

conversion is made available on the data pin.

Each DRDY falling edge starts the output of the new ADC

conversion data. The first eight bits output after the DRDY falling

edge are the header bits; the last 24 bits are the ADC conversion

result.

Figure 97, Figure 98, and Figure 99 are distinct examples of the

impact of the FORMATx pins on the AD7768 output operating in

standard conversion operation. Figure 100 and Figure 101 show

two examples of the AD7768-4 interface configuration.

Figure 97 to Figure 99 represent running the AD7768 at

maximum data rate for the three FORMATx options.

Figure 97 shows FORMATx = 00 each ADC has its own data

out pin running at the MCLK/4 bit rate. In pin control mode, this is

achieved by selecting Mode 0xA (fast mode, DCLK = MCLK/4,

standard conversion, see Table 20) with the decimation rate set as

×32.

Figure 98 shows FORMATx = 01 share DOUT1 at the maximum

bit rate. In pin control mode, this is achieved by selecting Mode 0x8

(fast mode, DCLK = MCLK/1, standard conversion) with a

decimation rate of ×32.

If running in pin control mode, the example shown in Figure 99

represents Mode 0x4 (median mode, DCLK = MCLK/1,

standard conversion) with a decimation rate of ×32, giving the

maximum output data capacity possible on one DOUTx pin.

DCLK

DRDY

SAMPLE N

SAMPLE N + 1

D31

D28

D30 D29

D27

DOUT0

D...

D31

D28

D30 D29

D27

D...

DOUT1

D31

D28

D30 D29

D27

D31

D28

D30 D29

D27

D...

DOUT7

D31

D28

D30 D29

D27

D31

D28

D30 D29

D27

Figure 97. AD7768 FORMATx = 00: Each ADC Has a Dedicated Data Output Pin, Maximum Data Rate

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