AD7768 datasheet(12/99 Pages) AD

12 / 99 page

AD7768/AD7768-4

Data Sheet

Rev. A | Page 12 of 99

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Sinc5 Filter

Fast

AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,

reference precharge buffers off

168

AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,

reference precharge buffers on

248

AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =

3.6 V, reference precharge buffers off

265

291

Median

AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,

reference precharge buffers off

AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,

reference precharge buffers on

137

AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =

3.6 V, reference precharge buffers off

150

167

Eco

AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,

reference precharge buffers off

AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,

reference precharge buffers on

AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =

3.6 V, reference precharge buffers off

Standby Mode

All channels disabled (sinc5 filter enabled),

AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V2

AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V2

AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V

Sleep Mode2

Full power-down (SPI control mode),

AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V

1.8

AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V

2.5

AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V

2.7

6.5

The output data rate ranges refer to the programmable decimation rates available on the AD7768/AD7668-4 for a fixed MCLK rate of 32.768 MHz. Varying MCLK rates

allow users a wider variation of ODR.

These specifications are not production tested but are supported by characterization data at initial product release.

See the Terminology section for more information about the fa and fb input frequencies.

Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration

reduces the gain error to the order of the noise for the programmed output data rate.

−25 µA is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common-mode voltage approaches (AVDD1 −

AVSS)/2. The analog input current scales with the MCLK frequency and device power mode. See Figure 85 and Figure 86 for more details on how the analog input

current scales with input voltage.

For lower MCLK rates or higher decimation rates, use Table 35 and Table 36 to calculate any additional delay before the first DRDYE pulse.

The RESETE pin has an internal pull-up device to IOVDD.

Configuring Channel Mode A to the sinc5 filter and/or assigning disabled channels to Channel Mode A allows a lower power consumption to be achieved. To do this,

the user must be operating in SPI control mode because it requires assigning channels to different channel modes (only possible in SPI control mode). If using pin

control mode, all channels, whether active or in standby, are assigned to the same channel group and use the same filter type. This means that, in pin control mode, a

higher current consumption is seen from disabled channels than can be achieved in SPI mode. See the Channel Modes section for more details.

1.8 V IOVDD SPECIFICATIONS

AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 1.72 V to 1.88 V, AVSS = DGND = 0 V, REFx+ =

4.096 V and REFx− = 0 V, MCLK = 32.76 8 MHz, analog precharge buffers on, reference precharge buffers off, wideband filter, fCHOP =

fMOD/32, TA = −40°C to +105°C, unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

For dynamic range and SNR across all decimation

rates, see Table 12 and Table 13

Fast

Decimation by 32, 256 kSPS ODR

Dynamic Range

Shorted input, wideband filter

106.2

108

SNR

Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input

109

111

Wideband filter, 1 kHz, −0.5 dBFS, sine wave input

106

107.8

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