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AD7768 Datasheet(PDF) 17 Page - Analog Devices |
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AD7768 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 99 page  Data Sheet AD7768/AD7768-4 Rev. A | Page 17 of 99 Parameter Description Test Conditions/Comments Min Typ Max Unit t28 SCLK disable time 0 ns t29 CS high time 10 ns t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns fMOD = MCLK/8 2.2 × tMCLK ns fMOD = MCLK/32 8.8 × tMCLK ns 1 These specifications are not production tested but are supported by characterization data at initial product release. 1.8 V IOVDD TIMING SPECIFICATIONS AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 1.72 V to 1.88 V (DREGCAP tied to IOVDD), Input Logic 0 = DGND, Input Logic 1 = IOVDD, CLOAD = 10 pF on DCLK pin, CLOAD = 20 pF on other digital outputs, TA = −40°C to +105°C. tODR is 1/ODR. Table 5. Data Interface Timing1 Parameter Description Test Conditions/Comments Min Typ Max Unit MCLK Master clock 1.15 34 MHz fMOD Modulator frequency Fast mode MCLK/4 Hz Median mode MCLK/8 Hz Eco mode MCLK/32 Hz t1 DRDY high time tDCLK − 10% 28 ns t2 DCLK rising edge to DRDY rising edge 2 ns t3 DCLK rising to DRDY falling −4.5 0 ns t4 DCLK rise to DOUTx valid 2.0 ns t5 DCLK rise to DOUTx invalid −4 ns t6 DOUTx valid to DCLK falling 8.5 tDCLK/2 ns t7 DCLK falling edge to DOUTx invalid 8.5 tDCLK/2 ns t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns t8a = DCLK = MCLK/2 tMCLK ns t8b = DCLK = MCLK/4 2 × tMCLK ns t8c = DCLK = MCLK/8 4 × tMCLK ns t9 DCLK low time DCLK=MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 (tDCLK/2 ns t9a = DCLK = MCLK/2 tMCLK ns t9b = DCLK = MCLK/4 2 × tMCLK ns t9c = DCLK = MCLK/8 4 × tMCLK ns t10 MCLK rising to DCLK rising CMOS clock 37 ns t11 Setup time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768, DIN on the AD7768-4 14 ns t12 Hold time (daisy-chain inputs) DOUT6 and DOUT7 on the AD7768, DIN on the AD7768-4 0 ns t13 START low time 1 × tMCLK ns t14 MCLK to SYNC_OUT valid CMOS clock SYNC_OUT RETIME_EN bit disabled; measured from falling edge of MCLK 10 31 ns SYNC_OUT RETIME_EN bit enabled; measured from rising edge of MCLK 15 37 ns t15 SYNC_IN setup time CMOS clock 0 ns t16 SYNC_IN hold time CMOS clock 11 ns 1 These specifications are not production tested but are supported by characterization data at initial product release. |
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