AD7768 datasheet(66/99 Pages) AD

66 / 99 page

AD7768/AD7768-4

Data Sheet

Rev. A | Page 66 of 99

Data Interface: One-Shot Conversion Operation

One-shot mode is available in both SPI and pin control modes.

This conversion mode is available by selecting one of Mode 0xC to

Mode 0xF when in pin control mode. In SPI control mode, set

Bit 4 (one shot) of Register 0x06, the data control register.

Figure 103 shows the device operating in one-shot mode.

In one-shot mode, the AD7768/AD7768-4 are pseudo slaves.

Conversions occur on request by the master device, for example,

the DSP or FPGA. The SYNC_IN pin initiates the conversion

request. In one-shot mode, all ADCs run continuously; however,

the rising edge of the SYNC_IN pin controls the point in time

from which data is output.

To receive data, the master must pulse the SYNC_IN pin to

reset the filter and force DRDY low. DRDY subsequently goes

high to indicate to the master device that the device has valid

settled data available. Unlike standard mode, DRDY remains

high for the number of clock periods of valid data before it goes

low again; thus, in this conversion mode, it is an active high

frame of the data.

When the master pulses SYNC_IN and the AD7768/AD7768-4

receive the rising edge of this signal, the digital filter is reset and

the full settling time of the filter elapses before the data is available.

The duration of the settling time depends on the filter path and

decimation rate. Running one-shot mode with the sinc5 filter

allows the fastest throughput, because this filter has a lower

settling time than the wideband filter.

As soon as settled data is available on any channel, the device

outputs data from all channels. The contents of Bit 6 of the channel

header status bits indicates whether the data is fully settled.

The period before the data is settled on all channels (tSETTLE) is

shown in Figure 103. After the data has settled on all channels,

DRDY is asserted high and the device outputs the required settled

data on all channels before DRDY is asserted low. If the user config-

ures the same filter and decimation rate on each ADC, the data is

settled for all channels on the first DRDY output frame, which

avoids a period of unsettled data prior to the settled data and

ensures that all data is output at the same time on all ADCs. The

device then waits for another SYNC_IN signal before outputting

more data.

Because all the ADCs are sampling continuously, one-shot mode

affects the sampling theory of the AD7768/AD7768-4. Particularly,

a user periodically sending a SYNC_IN pulse to the device is a

form of subsampling of the ADC output. The subsampling occurs

at the rate of the SYNC_IN pulses. The SYNC_IN pulse must be

synchronous with the master clock to ensure coherent sampling

and to reduce the effects of jitter on the frequency response.

Daisy-Chaining

Daisy-chaining devices allows numerous devices to use the

same data interface lines by cascading the outputs of multiple

ADCs from separate AD7768/AD7768-4 devices. Only one

ADC device has its data interface in direct connection with the

digital host.

For the AD7768/AD7768-4, this connection can be implemented

by cascading DOUT0 and DOUT1 through a number of devices,

or just using DOUT0; whether two data output pins or only one

data output pin is enabled depends on the FORMATx pins. The

ability to daisy-chain devices and the limit on the number of

devices that can be handled by the chain is dependent on the

power mode, DCLK, and the decimation rate employed.

The maximum usable DCLK frequency allowed when daisy-

chaining devices is limited by the combination of timing

specifications in Table 3 or Table 5, as well as by the propagation

delay of the data between devices and any skew between the MCLK

signals at each AD7768/AD7768-4 device. The propagation delay

and MCLK skew are dependent on the PCB layout and trace

lengths.

This feature is especially useful for reducing component count

and wiring connections, for example, in isolated multiconverter

applications or for systems with a limited interfacing capacity.

When daisy-chaining, on the AD7768, DOUT6 and DOUT7

become serial data inputs, and DOUT0 and DOUT1 remain as

serial data outputs under the control of the FORMATx pins. For

the AD7768-4 the DIN pin is the daisy chain serial data input

pin and DOUT0 is the serial data output pin.

START

SYNC_IN

DOUT1

DOUT0

DRDY

DOUT6

MCLK

DOUT7

SYNC_OUT

DSP/

FPGA

START

SYNC_IN

DOUT1

DOUT0

DRDY

DOUT6

MCLK

DOUT7

SYNC_OUT

DNC

IOVDD

START

SYNC_IN

DOUT1

DOUT0

DRDY

DOUT6

MCLK

DOUT7

SYNC_OUT

DNC

AD7768

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

MASTER

CLOCK

Figure 104. Daisy-Chaining Multiple AD7768 Devices

Figure 104 shows an example of daisy-chaining AD7768 devices,

when FORMATx = 01. In this case, the DOUT1 and DOUT0

pins of the AD7768 devices are cascaded to the DOUT6 and

DOUT7 pins of the next device in the chain. Data readback is

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