AD7768 datasheet(52/99 Pages) AD

52 / 99 page

AD7768/AD7768-4

Data Sheet

Rev. A | Page 52 of 99

Clocking Selections

The internal modulator frequency (fMOD) that is used by each of

the ADCs in the AD7768/AD7768-4 is derived from the

externally applied MCLK signal. The MCLK division bits allow

the user to control the ratio between the MCLK frequency and

the internal modulator clock frequency. This control allows the

user to select the division ratio that is best for their configuration.

The appropriate clock configuration depends on the power

mode, the decimation rate, and the base MCLK frequency

available in the system. See the Clocking, Sampling Tree section

for further information on setting MCLK_DIV correctly.

MCLK Source Selection

The following clocking options are available as the MCLK input

source in SPI control mode:

•

LVDS

•

External crystal

•

CMOS input MCLK

Setting CLK_SEL to logic low configures the AD7768/AD7768-4

for correct operation using a CMOS clock. Setting CLK_SEL to

logic high enables the use of an external crystal.

If CLK_SEL is set to logic high and Bit 3 of Register 0x04 is also

set, the application of an LVDS clock signal to the MCLK pin is

enabled. LVDS clocking is exclusive to SPI control mode and

requires the register selection for operation (see Table 42 for the

AD7768 or Table 68 for the AD7768-4).

The DCLK rate is derived from MCLK. DCLK division (the

ratio between MCLK and DCLK) is controlled in the interface

configuration selection register, Register 0x07 (see Table 45 for

the AD7768 or Table 71 for the AD7768-4).

Interface Configuration

The data interface is a master output interface, where ADC

conversion results are output by the AD7768/AD7768-4 at a

rate based on the mode selected. The interface consists of a data

clock (DCLK), the data ready (DRDY) framing output, and the

data output pins (DOUT0 to DOUT7 for the AD7768, DOUT0

to DOUT3 for the AD7768-4).

On the AD7768, the interface can be configured to output

conversion data on one, two, or eight of the DOUTx pins. The

DOUTx configuration for the AD7768 is selected using the

FORMATx pins (see Table 31).

On the AD7768-4, the interface can be configured to output

conversion data on one or four of the DOUTx pins. The

DOUTx configuration for the AD7768-4 is selected using

the FORMAT0 pin (see Table 32).

The DCLK rate is a direct division of the MCLK input and can

be controlled using Bits[1:0] of Register 0x07. The minimum

DCLK rate can be calculated as

DCLK (minimum) = Output Data Rate × Channels per

DOUTx × 32 bits

where MCLK ≥ DCLK.

With eight ADCs enabled, an MCLK rate of 32.768 MHz, an ODR

of 256 kSPS, and two DOUTx channels, DCLK (minimum) is

256 kSPS × 4 channels per DOUTx × 32 bits = 32.768 MHz

where DCLK = MCLK/1.

For more information on the status header, CRC, and interface

configuration, see the Data Interface section.

CRC Protection

The AD7768/AD7768-4 can be configured to output a CRC

message per channel every 4 or 16 samples. This function is

available only with SPI control. CRC is enabled in the interface

control register, Register 0x07 (see the CRC Check on Data

Interface section).

ADC Synchronization over SPI

The ADC synchronization over SPI allows the user to request a

synchronization pulse to the ADCs over the SPI interface. To

initiate the synchronization in this manner, write to Bit 7 in

First, the user must write a 0, which sets SYNC_OUT low, and

then write a 1 to set the SYNC_OUT logic high again.

The SPI_SYNC command is recognized after the last rising edge of

SCLK in the SPI instruction, where the SPI_SYNC bit is changed

from low to high. The SPI_SYNC command is then output synchro-

nously to the AD7768/AD7768-4 MCLK signal on the

SYNC_OUT pin. The user must connect the SYNC_OUT signal

to the SYNC_IN pin on the PCB.

START

SYNC_IN

DOUTx

DRDY

MCLK

SPI INTERFACE

SYNC_OUT

DSP/

FPGA

AD7768/

AD7768-4

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

MASTER

CLOCK

IOVDD

Figure 81. Connection Diagram for Synchronization Using SPI_SYNC

The SYNC_OUT pin can also be routed to the SYNC_IN pins of

other AD7768/AD7768-4 devices, allowing simultaneous

sampling to occur across larger channel count systems. Any

daisy-chained system of AD7768/AD7768-4 devices requires that

all ADCs be synchronized.

In a daisy-chained system of AD7768/AD7768-4 devices, two

successive synchronization pulses must be applied to guarantee

that all ADCs are synchronized. Two synchronization pulses are

also required in a system of more than one AD7768/AD7768-4

device sharing a single MCLK signal, where the DRDY pin of

only one device is used to detect new data.

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