AD7768 datasheet(89/99 Pages) AD

89 / 99 page

Data Sheet

AD7768/AD7768-4

Rev. A | Page 89 of 99

CHANNEL MODE B REGISTER

Address: 0x02, Reset: 0x0D, Name: Channel Mode B

Table 66. Bit Descriptions for Channel Mode B

Bits

Bit Name

Settings

Description

Reset

Access

FILTER_TYPE_B

Filter selection

0x1

Wideband filter

Sinc5 filter

[2:0]

DEC_RATE_B

Decimation rate selection

0x5

000

×32

001

×64

010

×128

011

×256

100

×512

101

×1024

110

×1024

111

×1024

CHANNEL MODE SELECT REGISTER

Address: 0x03, Reset: 0x00, Name: Channel Mode Select

This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.

Table 67. Bit Descriptions for Channel Mode Select

Bits

Bit Name

Settings

Description

Reset

Access

CH_3_MODE

Channel 3

0x0

Mode A

Mode B

CH_2_MODE

Channel 2

0x0

Mode A

Mode B

CH_1_MODE

Channel 1

0x0

Mode A

Mode B

CH_0_MODE

Channel 0

0x0

Mode A

Mode B

POWER MODE SELECT REGISTER

Address: 0x04, Reset: 0x00, Name: POWER_MODE

Table 68. Bit Descriptions for POWER_MODE

Bits

Bit Name

Settings

Description

Reset

Access

SLEEP_MODE

In sleep mode, many of the digital clocks are disabled and all of the ADCs

are disabled. The analog LDOs are not disabled.

0x0

The AD7768-4 SPI is live and is available to the user. Writing to this bit

brings the AD7768-4 out of sleep mode again.

Normal operation.

Sleep mode.

AD7768 Datasheet(PDF) 89 Page - Analog Devices

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