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Data Sheet

AD9684

Rev. 0 | Page 43 of 64

LOW-PASS

FILTER

REAL

HB1 FIR

LOW-PASS

FILTER

HB1 FIR

COMPLEX TO

REAL ENABLE

90°

0°

–

COMPLEX TO REAL CONVERSION

GAIN STAGE

cos(wt)

sin(wt)

fS/4

I/REAL

0dB

6dB

0dB

6dB

0dB

6dB

0dB

6dB

Figure 66. Complex to Real Conversion Block

DDC EXAMPLE CONFIGURATIONS

Table 22 describes the register settings for multiple DDC example configurations.

Table 22. DDC Example Configurations

Chip

Application

Layer

Chip

Decimation

Ratio

DDC Input

Type

DDC

Output

Type

Bandwidth

Per DDC1

Number of Virtual

Converters

Required (M)

One DDC

Complex

77% × fS

selected)

by 2)

0 dB gain, variable IF, complex outputs,

HB1 filter)

ADC Channel A, DDC Q input = ADC

Channel B)

and POW set as required by application

for DDC 0

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