AD9684 datasheet(9/64 Pages) AD

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Data Sheet

AD9684

Rev. 0 | Page 9 of 64

D13

CLK+

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

90° PHASE ADJUST1

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

270° PHASE ADJUST2

SYNC+

APERTURE DELAY

N + x

N – 1

N + y

N + 35

N + 36

N + 37

N + 38

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

D0±

D13±

FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE

CONVERTER 0

SAMPLE

[N]

N + 39

N + 40

N + 41

VIN±x

190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

STATUS

D13

STATUS

D13

STATUS

D13

STATUS

D13

STATUS

D13

STATUS

CLK–

SYNC–

STATUS+

(OVERRANGE/STATUS BIT)

STATUS–

tCLK

tDCO

tPD

tSKEWR

CONVERTER 0

SAMPLE

[N + 1]

CONVERTER 0

SAMPLE

[N + 2]

CONVERTER 0

SAMPLE

[N + 3]

CONVERTER 0

SAMPLE

[N + 4]

tSKEWF

CONSTANT LATENCY = X CLK CYCLES

Figure 4. Parallel Interleaved Mode—One Converter, ≤14-Bit Data

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