AD9684 datasheet(13/64 Pages) AD

13 / 64 page

Product

Overview

Online

Documentation

Design

Resources

Discussion

Sample

& Buy

Data Sheet

AD9684

Rev. 0 | Page 13 of 64

D15

CLK+

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

90° PHASE ADJUST1

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

270° PHASE ADJUST2

SYNC+

STATUS–

(FRAME CLOCK OUTPUT)3

STAUS+

STATUS+

(OVERRANGE STATUS BIT)

STATUS–

APERTURE DELAY

N + x

N – 1

N + y

N + z

N + 36

N + 37

N + 38

D0±

D7±

I0[N]

EVEN

N + 39

N + 40

N + 41

N + 42

VIN±x

190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

3FRAME CLOCK OUTPUT SUPPORTS 3 MODES OF OPERATION:

1) ENABLED (ALWAYS ON).

2) DISABLED (ALWAYS OFF).

3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDO-RANDOM BIT).

4STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP.

PAR4

D15

PAR

D14

STATUS

D15

PAR

D14

STATUS

D15

PAR

D14

STATUS

D15

PAR

D14

STATUS

D15

PAR

CLK–

FRAME 0

FRAME 1

SYNC–

tCLK

tDCO

CONSTANT LATENCY = X CLK CYCLES

tSTATUS

tPD

tFRAME

I0[N]

ODD

Q0[N]

EVEN

Q0[N]

ODD

I0[N + 1]

EVEN

I0[N + 1]

ODD

Q0[N + 1]

EVEN

Q0[N + 1]

ODD

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

FIXED DELAY FROM SYNC EVENT

TO DCO KNOWN PHASE

tSKEWF

tSKEWR

Figure 8. LVDS Byte Mode—Two Virtual Converters, One DDC, I/Q Data Decimate by 4

AD9684 Datasheet(PDF) 13 Page - Analog Devices

AD9684 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL