AD9684 datasheet(1/64 Pages) AD

Part #	AD9684

Description	Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter

PDF	64 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V,

Analog-to-Digital Converter

Data Sheet

AD9684

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Parallel LVDS (DDR) outputs

1.1 W total power per channel at 500 MSPS (default settings)

SFDR = 85 dBFS at 170 MHz fIN (500 MSPS)

SNR = 68.6 dBFS at 170 MHz fIN (500 MSPS)

ENOB = 10.9 bits at 170 MHz fIN

DNL = ±0.5 LSB

INL = ±2.5 LSB

Noise density = −153 dBFS/Hz at 500 MSPS

1.25 V, 2.50 V, and 3.3 V supply operation

No missing codes

Internal analog-to-digital converter (ADC) voltage reference

Flexible input range and termination impedance

1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)

400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

SYNC± input allows multichip synchronization

DDR LVDS (ANSI-644 levels) outputs

2 GHz usable analog input full power bandwidth

>96 dB channel isolation/crosstalk

Amplitude detect bits for efficient AGC implementation

Two integrated wideband digital processors per channel

12-bit numerically controlled oscillator (NCO)

3 cascaded half-band filters

Differential clock inputs

Serial port control

Integer clock divide by 2, 4, or 8

Small signal dither

APPLICATIONS

Communications

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE

General-purpose software radios

Ultrawideband satellite receiver

Instrumentation (spectrum analyzers, network analyzers,

integrated RF test solutions)

Radar

Digital oscilloscopes

High speed data acquisition systems

DOCSIS CMTS upstream receiver paths

HFC digital reverse path receivers

FUNCTIONAL BLOCK DIAGRAM

VIN+A

VIN–A

AD9684

CLOCK

GENERATION

BUFFER

VIN+B

VIN–B

SIGNAL MONITOR

FAST

DETECT

BUFFER

D0±

16

D1±

D2±

D3±

D4±

D5±

D6±

D7±

D8±

D9±

D10±

D11±

D12±

D13±

DCO±

STATUS±

ADC

CORE

ADC

CORE

SPI CONTROL

AGND

SDIO

SCLK

CSB

DGND

DRGND

PDWN/

STBY

SPIVDD

(1.8V TO 3.4V)

DRVDD

(1.25V)

DVDD

(1.25V)

AVDD3

(3.3V)

AVDD2

(2.5V)

AVDD1

(1.25V)

FD_A

FD_B

V_1P0

CLK+

CLK–

÷2

÷4

÷8

14

DIGITAL

DOWN-

CONVERTER

DIGITAL

DOWN-

CONVERTER

CONTROL

REGISTERS

SYNC–

SYNC+

Figure 1.

GENERAL DESCRIPTION

The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has

an on-chip buffer and a sample-and-hold circuit designed for

low power, small size, and ease of use. This product is designed

for sampling wide bandwidth analog signals. The AD9684 is

optimized for wide input bandwidth, a high sampling rate,

excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth buffered inputs, supporting a

variety of user selectable input ranges. An integrated voltage

reference eases design considerations. Each ADC data output is

internally connected to an optional decimate by 2 block.

The analog input and clock signals are differential inputs. Each

ADC data output is internally connected to two digital

downconverters (DDCs). Each DDC consists of four cascaded

signal processing stages: a 12-bit frequency translator (NCO),

and three half-band decimation filters supporting a divide by

factor of two, four, and eight.

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