AD9684 datasheet(25/64 Pages) AD

25 / 64 page

Product

Overview

Online

Documentation

Design

Resources

Discussion

Sample

& Buy

Data Sheet

AD9684

Rev. 0 | Page 25 of 64

Input Common Mode

The analog inputs of the AD9684 are internally biased to the

common mode as shown in Figure 41. The common-mode

buffer has a limited range in that the performance suffers greatly

if the common-mode voltage drops by more than 100 mV.

Therefore, in dc-coupled applications, set the common-mode

voltage to 2.05 V ± 100 mV to ensure proper ADC operation.

Analog Input Controls and SFDR Optimization

The AD9684 offers flexible controls for the analog inputs, such

as input termination and buffer current. All of the available

controls are shown in Figure 41.

10pF

VIN+x

VIN–x

AVDD3

VCM

BUFFER

400Ω

3pF

AIN CONTROL

(SPI) REGISTERS

(REG 0x008, REG 0x015,

REG 0x016, REG 0x018,

REG 0x025)

Figure 41. Analog Input Controls (Should the AIN

Using Register 0x018, the buffer currents on each channel can

be scaled to optimize the SFDR over various input frequencies

and bandwidths of interest. As the input buffer currents are set,

the amount of current required by the AVDD3 supply changes.

For a complete list of buffer current settings, see Table 29.

110

130

150

170

190

210

230

250

1.5×

2.5×

3.5×

4.5×

5.5×

6.5×

7.5×

8.5×

BUFFER CURRENT SETTING

Figure 42. AVDD3 Power (IAVDD3) vs. Buffer Current Control Setting in

100

150

200

250

300

1.0×

1.5×

2.0×

3.0×

350

400

450

500

INPUT FREQUENCY (MHz)

4.5×

Figure 43. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF),

10 MHz < fIN < 500 MHz

500

550

600

650

700

750

800

850

900

950

1000

INPUT FREQUENCY (MHz)

4.5×

5.0×

6.0×

7.0×

8.0×

Figure 44. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF),

500 MHz < fIN < 1000 MHz

1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

INPUT FREQUENCY (MHz)

4.5×

5.0×

6.0×

7.0×

8.0×

Figure 45. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF),

1 GHz < fIN < 2 GHz, Front-End Network Shown in Figure 40

Figure 43, Figure 44, and Figure 45 show how the SFDR can be

optimized using the buffer current setting in Register 0x018 for

different Nyquist zones. At frequencies greater than 1 GHz, it is

better to run the ADC at input amplitudes less than −1 dBFS

(−3 dBFS, for example). This greatly improves the linearity of

the converted signal without sacrificing SNR performance.

AD9684 Datasheet(PDF) 25 Page - Analog Devices

AD9684 Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL