PCI9060 datasheet(76/192 Pages) ETC

76 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 67

Version 1.02

4.4.7 (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region

Descriptor Register

Table 4-39. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Register

Field

Description

Read

Write

Value after Reset

1:0

Memory Space 0 Local Bus Width. Value of 00 indicates bus width of 8 bits, a value

of 01 indicates bus width of 16 bits and a value of 10 or 11 indicates bus width of

32 bits.

Yes

S = 01

J = 11

C = 11

5:2

Memory Space 0 Internal Wait States (data to data; 0-15 wait states).

Yes

Memory Space 0 Ready Input Enable. Value of 1 enables Ready input. Value of 0

disables Ready input.

Yes

Memory Space 0 BTERM# Input Enable. Value of 1 enables BTERM# input. Value

of 0 disables BTERM# input. If this bit is set to 0, PCI 9080 bursts four Lword

maximum at a time.

Yes

Memory Space 0 Prefetch Disable. If mapped into memory space, a value of 0

enables read prefetching. Value of 1 disables prefetching. If prefetching is disabled,

PCI 9080 disconnects after each memory read.

Yes

Expansion ROM Space Prefetch Disable. Value of 0 enables read prefetching.

Value of 1 disables prefetching. If prefetching is disabled, PCI 9080 disconnects

after each memory read.

Yes

Read Prefetch Count Enable. When set to 1 and memory prefetching is enabled,

PCI 9080 prefetches up to the number of Lwords specified in the prefetch count.

When set to 0, PCI 9080 ignores the count and continues prefetching until

terminated by the PCI bus.

Yes

14:11

Prefetch Counter. Number of Lwords to prefetch during memory read cycles (0-15).

A count of zero selects a prefetch of 16 Lwords.

Yes

Reserved.

Yes

17:16

Expansion ROM Space Local Bus Width. Value of 00 indicates bus width of 8 bits,

a value of 01 indicates bus width of 16 bits and a value of 10 or 11 indicates bus

width of 32 bits.

Yes

S = 01

J = 11

C = 11

21:18

Expansion ROM Space Internal Wait States (data to data; 0-15 wait states).

Yes

Expansion ROM Space Ready Input Enable. Value of 1 enables Ready input. Value

of 0 disables Ready input.

Yes

Expansion ROM Space BTERM# Input Enable. Value of 1 enables BTERM# input.

Value of 0 disables BTERM# input. If this bit is set to 1, PCI 9080 bursts four Lword

maximum at a time.

Yes

Memory Space 0 Burst Enable. Value of 1 enables bursting. Value of 0 disables

bursting. If burst is disabled, the local bus performs continuous single cycles for

burst PCI read/write cycles.

Yes

Extra Long Load from serial EEPROM. Value of 1 loads the Subsystem ID and

Local Address Space 1 registers. Value of 0 indicates not to load them.

Yes

Expansion ROM Space Burst Enable. Value of 1 enables bursting. Value of 0

disables bursting. If burst is disabled, the local bus performs continuous single

cycles for burst PCI read/write cycles.

Yes

Direct Slave PCI Write Mode. Value of 0 indicates PCI 9080 should disconnect

when the Direct Slave write FIFO is full. Value of 1 indicates PCI 9080 should de-

assert TRDY# when the write FIFO is full.

Yes

31:28

PCI Target Retry Delay Clocks. Contains the value (multiplied by 8) of the number

of PCI bus clocks after receiving a PCI local read or write access and not

successfully completing a transfer. Only pertains to Direct Slave writes when bit 27

is set to 1.

Yes

(32 clocks)

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