PCI9060 datasheet(80/192 Pages) ETC

80 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 71

Version 1.02

4.4.14 (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap)

Table 4-46. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Register

Field

Description

Read

Write

Value after Reset

Space 1 Enable. Value of 1 enables decoding of PCI addresses for Direct Slave

access to local space 1. Value of 0 disables decoding. If this bit is set to 0, the PCI

BIOS may not allocate (assign) the base address for Space 1.

Note:

Must be set to 1 for any Direct Slave access to Space 1.

Yes

Reserved.

Yes

3:2

If local space 1 is mapped into memory space, bits are not used. If mapped into

I/O space, bit is included with bits [31:4] for remapping.

Yes

31:4

Remap of PCI Address to Local Address Space 1 into a Local Address Space. The

bits in this register remap (replace) the PCI Address bits used in decode as the

Local Address bits.

Yes

Note:

Remap Address value must be multiple of Range (not the Range register).

4.4.15 (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register

Table 4-47. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register

Field

Description

Read

Write

Value after Reset

1:0

Memory Space 1 Local Bus Width. Value of 00 indicates bus width of 8 bits, a value

of 01 indicates bus width of 16 bits and a value of 10 or 11 indicates bus width of 32

bits.

Yes

S = 01

J = 11

C = 11

5:2

Memory Space 1 Internal Wait States (data to data; 0-15 wait states).

Yes

Memory Space 1 Ready Input Enable. Value of 1 enables Ready input. Value of 0

disables Ready input.

Yes

Memory Space 1 BTERM# Input Enable. Value of 1 enables BTERM# input. Value

of 0 disables BTERM# input. If this bit is set to 0, PCI 9080 bursts four Lword

maximum at a time.

Yes

Memory Space 1 Burst Enable. Value of 1 enables bursting. Value of 0 disables

bursting. If burst is disabled, the local bus performs continuous single cycles for

burst PCI read/write cycles.

Yes

Memory Space 1 Prefetch Disable. If mapped into memory space, 0 enables read

prefetching. Value of 1 disables prefetching. If prefetching is disabled, PCI 9080

disconnects after each memory read.

Yes

Read Prefetch Count Enable. When set to 1 and memory prefetching is enabled,

PCI 9080 prefetches up to the number of Lwords specified in the prefetch count.

When set to 0, PCI 9080 ignores the count is ignored and continues prefetching

until terminated by the PCI bus.

Yes

14:11

Prefetch Counter. Number of Lwords to prefetch during memory read cycles

(0-15).

Yes

31:15

Reserved.

Yes

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