DP83840A datasheet(39/89 Pages) NSC

39 / 89 page

3.0 Functional Description (Continued)

National Semiconductor

Version A

3.9.6 Auto-Negotiation Complete Time

This section describes the amount of time required to

complete an Auto-Negotiation cycle for the 840A. These

times are deﬁned for two cases. The ﬁrst case assumes

that the far end link partner does not support Auto-

Negotiation

and

either

ﬁxed

10M

100M

implementation.

Timer

Min spec

Max spec

840A

break link

1200ms

1500ms

1300ms

autoneg wait

500ms

1000ms

750ms

link fail inhibit

750ms

1000ms

800ms

------------------------------------------------------------------------------

Total

1700-2450ms

2500-3500ms

2050-2850ms

The second case assumes that the far end link partner fully

supports Auto-Negotiation:

Timer

Min spec

Max spec

840A

break link

1200ms

1500ms

1300ms

FLP bursts

104ms

312ms

200ms

link fail inhibit

750ms

1000ms

800ms

------------------------------------------------------------------------------

Total

1304-2054ms

1812-2812ms

1500-2300ms

Refer to chapter 28 of the IEEE 802.3u standard for a full

description of the individual timers related to Auto-

Negotiation.

3.10 RESET OPERATION

The DP83840A can be reset either by hardware or

software. A hardware reset may be accomplished either by

asserting the RESET pin (pin 44) during normal operation,

or upon powering up the device. A software reset is

accomplished by setting the reset bit in the Basic Mode

Control Register (bit 15, address 00h).

While either the hardware or software reset can be

implemented

any

time

after

device

initialization,

providing a hardware reset, as described in section

3.10.1, must be implemented upon device power-up/

initialization. Omitting the hardware reset operation

during the device power-up/initialization sequence can

result in improper device operation.

3.10.1 Power-up / Reset

When VCC is ﬁrst applied to the DP83840A it takes some

amount of time for power to actually reach the nominal 5V

potential. This initial power-up time can be referred to as a

VCC ramp when VCC is “ramping” from 0V to 5V. When the

initial VCC ramp reaches approximately 4V, the DP83840A

begins an internal reset operation which must be allowed

sufﬁcient time, relative to the assertion and deassertion of

the RESET pin, to reset the device. There are two methods

for guaranteeing successful reset upon device power-up.

The ﬁrst method accounts for those designs that utilize a

special power up circuit which, through hardware, will

assert the RESET pin upon power-up. In this case, the

deassertion (falling edge) of the RESET pin must not occur

until at least 500

µs after the time at which the V

CC ramp

initially reached the 4V point.

The second method accounts for those applications which

produce a reset pulse sometime after the initial power-up

of the device. In this case, it is recommended that a

positive pulse, with a duration of at least 1

µs, be applied to

the RESET pin no sooner than 500

µs after the point in time

where the initial VCC ramp reached 4V.

In both methods described above, it is important to note

that the logic levels present at each of the hardware

conﬁguration pins of the DP83840A (see list below) are

also latched into the device as a function of the reset

operation (either hardware or software). These hardware

conﬁguration values are guaranteed to be latched into the

DP83840A 2

µs after the deassertion of the RESET pin.

The hardware conﬁguration values latched into the

DP83840A during the reset operation are dependent on

the logic levels present at the following device pins upon

power-up:

During the power-up reset operation the LED1 through

LED5 pins are undeﬁned, the SPEED_10 pin will be

asserted, and the SPEED_100 pin will be deasserted.

3.10.2 Hardware Reset

A hardware Reset is accomplished by applying a positive

pulse, with a duration of at least 1

µs, to the RESET pin of

the DP83840A during normal operation. This will reset the

device such that all registers will be reset to default values

and the hardware conﬁguration values will be re-latched

into the device (similar to the power-up reset operation).

3.10.3 Software Reset

A software reset is accomplished by setting bit 15 of the

Basic Mode Control Register (address 00h). This bit is self

clearing and, when set, will return a value of “1” until the

software reset operation has completed. The software

reset will reset the device such that all registers will be

reset to default values and the hardware conﬁguration

values will be re-latched into the device (similar to the

power-up reset operation). Driver code should wait 500

µs

following a software reset before allowing further serial MII

operations with the DP83840A.

Pin #

Primary Function

Latched in at Reset

LBEN

PHYAD[0]

ENCSEL

PHYAD[1]

CRS

PHYAD[2]

PHYAD[3]

RX_ER

PHYAD[4]

AN0

AN1

REPEATER

10BTSER

BPALIGN

100

BP4B5B

BPSCR

DP83840A Datasheet(PDF) 39 Page - National Semiconductor (TI)

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