DP83840A datasheet(7/89 Pages) NSC

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2.0 Pin Description (Continued)

National Semiconductor

Version A

ENCSEL

(PHYAD[1])

I/O, J

ENCODE SELECT: Used to select binary or MLT-3 coding scheme in the PMD

transceiver (at the DP83223, logic high selects binary coding scheme and logic low

selects MLT-3 coding scheme).

This is also the PHY address sensing (PHYAD[1]) pin for multiple PHY applications-

-see Section 2.8 for more details.

LBEN

(PHYAD[0])

I/O, J

LOOPBACK ENABLE: For 100BASE-TX operation, this pin should be connected

to the Loopback Enable pin of a DP83223 100 Mb/s Transceiver:

1 = local 100BASE-TX transceiver Loopback enabled

0 = local 100BASE-TX transceiver Loopback disabled (normal operation)

This is also the PHY address sensing (PHYAD[0]) pin for multiple PHY applications-

-see Section 2.8 for more details.

This pin has no effect during 10 Mb/s operation.

TD-

TD+

O (ECL)

TRANSMIT DATA: Differential ECL 125 Mb/s serialized transmit data outputs to

the PMD transceiver (such as the DP83223).

SD-

SD+

I (ECL)

SIGNAL DETECT: Differential ECL signal detect inputs. Indicates that the PMD

transceiver has detected a receive signal from the twisted pair or fiber media.

RD-

RD+

I (ECL)

RECEIVE DATA: Differential ECL 125 Mb/s receive data inputs from the PMD

transceiver (such as the DP83223).

2.3 10 Mb/s INTERFACE

Signal Name

Type

Pin #

Description

REQ

EQUALIZATION RESISTOR: A resistor connected between this pin and GND or

VCC adjusts the equalization step amplitude on the 10BASE-T Manchester

encoded transmit data (TXU+/- or TXS+/-). Typically no resistor is required for

operation with cable lengths less than 100m. Great care must be taken to ensure

system timing integrity when using cable lengths greater than 100m. Refer to the

IEEE 802.3u standard, Clause 29 for more details on system topology issues.

This value must be determined empirically. Refer to section 3.7.8 for further detail.

RTX

EXTENDED CABLE RESISTOR: A resistor connected between this pin and GND

or VCC adjusts the amplitude of the differential transmit outputs (TXU+/- or TXS+/-

). Typically no resistor is required for operation with cable lengths less than 100m.

Great care must be taken to ensure system timing integrity when using cable

lengths greater than 100m. Refer to the IEEE 802.3u standard, Clause 29 for more

details on system topology issues.

This value must be determined empirically. Refer to section 3.7.8 for further detail.

TXU-

TXU+

UNSHIELDED TWISTED PAIR OUTPUT: This differential output pair sources the

10BASE-T transmit data and link pulses for UTP cable.

TXS-

TXS+

SHIELDED TWISTED PAIR OUTPUT: This differential output pair sources the

10BASE-T transmit data and link pulses for STP cable.

RXI-

RXI+

TWISTED PAIR RECEIVE INPUT: These are the differential 10BASE-T receive

data inputs for either STP or UTP.

2.2 100 Mb/s SERIAL PMD INTERFACE

I = TTL/CMOS input

O = TTL/CMOS output

Z = TRI-STATE output

J = IEEE 1149.1 pin

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