DP83840A datasheet(13/89 Pages) NSC

13 / 89 page

2.0 Pin Description (Continued)

National Semiconductor

Version A

2.8 PHY ADDRESS INTERFACE

The DP83840A PHYAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros

(00000) will result in a PHY isolation condition. See the Isolate bit description in the BMCR, address 00h, Section 4.2

for further detail.

Signal Name

Type

Pin #

Description

PHYAD[0]

(LBEN)

I/O, J

PHY ADDRESS [0]: PHY address sensing pin (bit 0) for multiple PHY

applications. PHY address sensing is achieved by strapping a pull-up/pull-down

resistor (typically 4.7 k

Ω) to this pin as required.

The pull-up/pull-down status of this pin is latched into the PHYAD address register

(address 19h) during power up/reset.

This pin is also the Loopback Enable output pin (LBEN) for the 100 Mb/s Serial

PMD Interface. See Section 2.2 for further detail.

PHYAD[1]

(ENCSEL)

I/O, J

PHY ADDRESS [1]: PHY address sensing pin (bit 1) for multiple PHY

applications. PHY address sensing is achieved by strapping a pull-up/pull-down

resistor (typically 4.7 k

Ω) to this pin as required.

The pull-up/pull-down status of this pin is latched into the PHYAD address register

(address 19h) during power up/reset.

This pin is also the Encode Select output pin (ENCSEL) for the 100 Mb/s Serial

PMD Interface. See Section 2.2 for further detail.

PHYAD[2]

(CRS)

I/O, Z, J

PHY ADDRESS [2]: PHY address sensing pin (bit 2) for multiple PHY

applications. PHY address sensing is achieved by strapping a pull-up/pull-down

resistor (typically 4.7 k

Ω) to this pin as required.

The pull-up/pull-down status of this pin is latched into the PHYAD address register

(address 19h) during power up/reset.

This pin is also the Carrier Sense output pin (CRS) for the MII Interface. See

Section 2.1 for further detail.

PHYAD[3]

(SPEED_100)

I/O, J

PHY ADDRESS [3]: PHY address sensing pin (bit 3) for multiple PHY

applications. PHY address sensing is achieved by strapping a pull-up/pull-down

resistor (typically 4.7 k

Ω) to this pin as required.

The pull-up/pull-down status of this pin is latched into the PHYAD address register

(address 19h) during power up/reset.

This pin is also the Speed 100 Mb/s output pin (SPEED_100) for optional control

of peripheral circuitry. See Section 2.2 for further detail.

PHYAD[4]

(RX_ER)

I/O, Z, J

PHY ADDRESS [4]: PHY address sensing pin (bit 4) for multiple PHY

applications. PHY address sensing is achieved by strapping a pull-up/pull-down

resistor (typically 4.7 k

Ω) to this pin as required.

The pull-up/pull-down status of this pin is latched into the PHYAD address register

(address 19h) during power up/reset.

This pin is also the Receive Error output pin (RX_ER) for the MII Interface. See

Section 2.1 for further detail.

2.9 MISCELLANEOUS

Signal Name

Type

Pin #

Description

RESET

I, J

RESET: Active high input that initializes or reinitializes the DP83840A. See

section 3.10 for further detail.

LOWPWR

I, J

LOW POWER MODE SELECT: Active high input that enables the low power

mode (100 Mb/s operation only). See section 3.13 for further detail.

I = TTL/CMOS input

O = TTL/CMOS output

Z = TRI-STATE output

J = IEEE 1149.1 pin

DP83840A Datasheet(PDF) 13 Page - National Semiconductor (TI)

DP83840A Datasheet(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Datasheet Download

Link URL