LM3421 datasheet(18/72 Pages) TI1

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FREQUENCY (Hz)

-20

-40

-60

-80

-45

-90

-135

-180

-225

-270

1e-1

1e1

1e3

1e5

1e7

GAIN

60°Phase Margin

PHASE

öP2

öP3

öP1

öZ1

P =

CMP

5 10

LM3421, LM3421-Q1, LM3423, LM3423-Q1

SNVS574F – JULY 2008 – REVISED JULY 2015

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Feature Description (continued)

To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the

crossover frequency. A simple compensator using a single capacitor at the COMP pin (CCMP) will add a dominant

pole to the system, which will ensure adequate phase margin if placed low enough. At high duty cycles (as

shown in Figure 17), the RHP zero places extreme limits on the achievable bandwidth with this type of

compensation. However, because an LED driver is essentially free of output transients (except catastrophic

failures open or short), the dominant pole approach, even with reduced bandwidth, is usually the best approach.

The dominant compensation pole (

ωP2) is determined by CCMP and the output resistance (RO) of the error

amplifier (typically 5 M

Ω) as demonstrated in Equation 16.

(16)

It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate

switching noise and, in some cases, provide better gain margin. This pole can be placed across RSNS to filter the

ESL of the sense resistor at the same time. Figure 18 shows how the compensation is physically implemented in

the system.

The high-frequency pole (

ωP3) can be calculated using Equation 17.

(17)

The total system transfer function becomes:

(18)

The resulting compensated loop gain frequency response shown in Figure 19 indicates that the system has

adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability.

Figure 19. Compensated Loop Gain Frequency Response

7.3.9 Start-Up Regulator

The LM34xx-Q1 includes a high voltage, low dropout bias regulator. When power is applied, the regulator is

enabled and sources current into an external capacitor (CBYP) connected to the VCC pin. The recommended

bypass capacitance for the VCC regulator is 2.2 µF to 3.3 µF. The output of the VCC regulator is monitored by an

internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the

supply is also internally current limited. Figure 20 shows the typical start-up waveforms for the LM34xx-Q1.

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Product Folder Links: LM3421 LM3421-Q1 LM3423 LM3423-Q1

LM3421 Datasheet(PDF) 18 Page - Texas Instruments

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