 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LM3421 Datasheet(PDF) 3 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
LM3421 Datasheet(HTML) 3 Page - Texas Instruments |
|
|
3 / 72 page  VCC 1 EN VIN OVP RCT FLT DPOL DDRV HSP AGND COMP CSH DAP RPD 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nDIM TIMR LRDY PGND GATE HSN IS 21 VIN OVP RCT AGND COMP CSH nDIM VCC 1 EN DDRV HSP DAP RPD 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PGND GATE HSN IS 17 LM3421, LM3421-Q1, LM3423, LM3423-Q1 www.ti.com SNVS574F – JULY 2008 – REVISED JULY 2015 5 Pin Configuration and Functions PWP Package PWP Package 16-Pin HTSSOP 20-Pin HTSSOP Top View Top View Pin Functions PIN I/O DESCRIPTION FUNCTION NAME LM3423 LM3421 Bypass with 100-nF capacitor to AGND as close to the device VIN 1 1 I Input voltage as possible in the printed-circuit-board layout. Connect to AGND for zero current shutdown or apply > 2.4 V EN 2 2 I Enable to enable device. COMP 3 3 I Compensation Connect a capacitor to AGND to set the compensation. Connect a resistor to AGND to set the signal current. For analog dimming, connect a controlled current source or a CSH 4 4 I Current sense high potentiometer to AGND as detailed in the Analog Dimming section. External RC network sets the predictive off-time and thus the RCT 5 5 I Resistor capacitor timing switching frequency. Connect to PGND through the DAP copper pad to provide AGND 6 6 GND Analog ground ground return for CSH, COMP, RCT, and TIMR. Connect to a resistor divider from VO to program output OVP 7 7 I Overvoltage protection overvoltage lockout (OVLO). Turnoff threshold is 1.24 V and hysteresis for turnon is provided by 23-µA current source. Connect a PWM signal for dimming as detailed in the PWM Dimming section and/or a resistor divider from VIN to program Dimming input / nDIM 8 8 I input undervoltage lockout (UVLO). Turnon threshold is 1.24 undervoltage protection V and hysteresis for turnoff is provided by a 23-µA current source. Connect to pullup resistor from VIN and N-channel MOSFET FLT 9 — I Fault flag open-drain output is high when a fault condition is latched by the timer. Connect a capacitor to AGND to set the time delay before a TIMR 10 — I Fault timer sensed fault condition is latched. Connect to pullup resistor from VIN and N-channel MOSFET LRDY 11 — O LED ready flag open-drain output pulls down when the LED current is not in regulation. Connect to AGND if dimming with a series P-channel DPOL 12 — I Dim polarity MOSFET or leave open when dimming with series N-channel MOSFET. DDRV 13 9 O Dim gate drive output Connect to the gate of the dimming MOSFET. Connect to AGND through the DAP copper pad to provide PGND 14 10 GND Power ground ground return for GATE and DDRV. GATE 15 11 O Main gate drive output Connect to the gate of the main switching MOSFET. VCC 16 12 I Internal regulator output Bypass with 2.2-µF to 3.3-µF ceramic capacitor to PGND. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM3421 LM3421-Q1 LM3423 LM3423-Q1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
