LM93 datasheet(25/92 Pages) NSC

25 / 92 page

14.0 SMBus Interface (Continued)

The master sends a repeated START.

The master sends the 7-bit slave address followed by a read bit (high).

The slave asserts an ACK.

The master receives the Byte Count (depends on the Fixed Block Command Code used) and asserts an ACK.

The master receives the first data byte and asserts an ACK.

10. The master continues to receive data bytes and asserting an ACK.

11. The master receives the last data byte.

12. The master asserts a NACK.

13. The master issues a STOP to end this transaction.

10 11

12 13

Slave

Address

Fixed

Block

Command

Code

(F2h–FDh)

Slave

Address

Byte

Count

(N)

Data

Byte 1

A Data

Byte N

Special Notes:

The LM93 returns 00h when address locations outside of normal address space are read.

Block reads do not wrap around from address FFh to 00h.

If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the master does not

acknowledge a byte.

If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the bus to allow the master

to issue a STOP signal.

14.5.4.6 I

2C Block Reads

The LM93 supports I

2C block reads. The following sequence of events occur in this transaction:

The master sends a START to start this transaction .

The master send 7-bit slave address followed by a write bit (low).

The slave asserts an ACK.

The master sends the register address and the slave asserts an ACK.

The master sends a repeated START.

The master sends the 7-bit slave address followed by a read bit (high).

The slave asserts an ACK.

The master receives Data Byte 1 and asserts an ACK.

The master continues to receive bytes and asserting an ACK for each byte received.

10. The master receives the last byte.

11. The master asserts a NACK.

12. The master issues a STOP.

A 10

Slave

Address

Slave

Address

Data

Byte 1

Data

Byte 2

A Data

Byte N

Special Notes:

The LM93 returns 00h when address locations outside of normal address space are read.

Block reads do not wrap around from address FFh to 00h.

If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the master does not

acknowledge a byte.

If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the bus to allow the master

to issue a STOP signal.

14.6 READING AND WRITING 16-BIT REGISTERS

Whenever the low byte of a 16-bit register is read, the high

byte is frozen. After the high byte is read, it is unfrozen. This

ensures that the entire 16-bit value is read properly and the

high byte matches with the low byte. If the low byte of a

different 16-bit register is read, the currently frozen high byte

is unfrozen and the high byte of the new 16-bit register is

frozen. In a system with two SMBus masters, it is very

important that only one master reads any 16-bit registers at

a time. One possible method to achieve this would involve

using 16-bit SMBus reads (instead of two separate 8-bit

reads) to read 16-bit registers.

LM93 Datasheet(PDF) 25 Page - National Semiconductor (TI)

LM93 Datasheet(HTML) 25 Page - National Semiconductor (TI)

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