LM93 datasheet(19/92 Pages) NSC

19 / 92 page

14.0 SMBus Interface (Continued)

telling the slave device to expect a block write, or it may

simply be a register address that tells the slave where sub-

sequent data is to be written.

Since data can flow in only one direction as defined by the

R/W bit, it is not possible to send a command to a slave

device during a read operation. Before doing a read opera-

tion, it is necessary to do a write operation to tell the slave

what sort of read operation to expect and/or the address

from which data is to be read.

When all data bytes have been read or written, stop condi-

tions are established. In WRITE mode, the master will allow

the data line to go high during the 10th clock pulse to assert

a STOP condition. In READ mode, the slave drives the data

not the master. For the bit in question, the slave is looking for

an acknowledge and the master doesn’t drive low. This is

known as ‘No Acknowledge’. The master then takes the data

line low during the low period before the 10th clock pulse,

then high during the 10th clock pulse to assert a STOP

condition.

Note, a repeated START may be given only between a write

and read operation that are in succession.

14.4 SMBUS ERROR SAFETY FEATURES

To provide a more robust SMBus interface, the LM93 incor-

porates a timeout feature for both SMBCLK and SMBDAT. If

either signal is low for a long period of time (see SMBus AC

specs), the LM93 SMBus state machine reverts to the idle

state and waits for a START signal. Large block transfers of

all zeros should be avoided if the SMBCLK is operating at a

very low frequency to avoid accidental timeouts. Pulling the

Reset pin low does not reset the SMBus state machine. If the

LM93 SMBDAT pin is low during a system reset, the LM93’s

state machine timeouts and resets automatically. If the

LM93’s SMBDAT pin is high during a system reset, the first

assertion of a start by the master resets the LM93’s interface

state machine.

Although it is a violation of the SMBus specification, in some

cases a START or STOP signal occurs in the middle of a

byte transfer instead of coming after an acknowledge bit. If

this occurs, only a partial byte was transferred. If a byte was

being written, it is aborted and the partial byte is not com-

mitted. If a byte was being read from a read-to-clear register,

the register is not cleared.

14.5 SERIAL INTERFACE PROTOCOLS

The LM93 contains volatile registers, the registers occupy

address locations from 00h to EFh.

Data can be read and written as a single byte, a word, or as

a block of several bytes. The LM93 supports the following

SMBus/I

2C transactions/protocols:

— Send Byte

— Write Byte

— Write Word

— SMBus Write Block

—I

2C Block Write

— Read Byte

— Read Word

— SMBus Read Block

— SMBus Block-Write Block-Read Process Call

—I

2C Block Read

In addition to these transactions the LM93 supports a few

extra items and also has some behavior that must be defined

beyond the SMBus 2.0 specification. No other SMBus 2.0

transactions are supported (PEC, ARA etc.).

The SMBus specification defines several protocols for differ-

ent types of read and write operations. The ones used in the

LM93 are discussed below. The following abbreviations are

used in the diagrams:

— START

— STOP

R — READ

W — WRITE

— ACKNOWLEDGE

/A — NO ACKNOWLEDGE

14.5.1 Address Incrementing

The established base address does not increment. Repeat-

edly reading without re-establishing a new base address

returns data from the same address each time. I

2C read

transactions can use this information and skip reestablishing

the base address, when only one master is used. One

exception to this rule exists when a block write and block

read is used to emulate a block write/read process call. This

is detailed later, see the Block Write/Read Process Call

description.

LM93 Datasheet(PDF) 19 Page - National Semiconductor (TI)

LM93 Datasheet(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL