LM93 datasheet(17/92 Pages) NSC

17 / 92 page

12.0 Functional Description

(Continued)

is configured to short the PROCHOT signals together, it

always asserts them together whenever this function is en-

abled.

12.12 FAN SPEED MEASUREMENT

The fan tach circuitry measures the period of the fan pulses

by enabling a counter for two periods of the fan tach signal.

The accumulated count is proportional to the fan tach period

and inversely proportional to the fan speed. All four fan tach

signals are measured within 1 second.

Fans in general do not over-speed if run from the correct

voltage, so the failure condition of interest is under speed

due to electrical or mechanical failure. For this reason only

low-speed limits are programmed into the limit registers for

the fans. It should be noted that, since fan period rather than

speed is being measured, a fan tach error event occurs

when the measurement exceeds the limit value.

12.13 SMART FAN SPEED MEASUREMENT

If a fan is driven using a low-side drive PWM, the tachometer

output of the fan is corrupted. The LM93 includes smart

tachometer circuitry that allows an accurate tachometer

reading to be achieved despite the signal corruption. In

smart tach mode all four signals are measured within 4

seconds.

A smart tach capture cycle works according to the following

steps:

Both PWM outputs are synchronized such that they

activate simultaneously.

Both PWM output active times are extended for up to 50

ms.

The number of tach signal periods during the 50 ms

interval are tracked:

a) If less than 1 period is sensed during the 50 ms exten-

sion the result returned is 3FFh.

b) After one period occurs the count for that period is

memorized.

c) If during the 50 ms interval 2 periods do not occur, the

tach value reported is the 1 period count multiplied by

d) If 2 periods do occur, the 2 period count is loaded into

the value register and the 50 ms PWM extension is

terminated.

The lowest two bits in each of the Fan Tach value registers

are reserved. The smart tach feature takes advantage of

these bits. In normal tach mode, these bits return 00. In

smart tach mode the two bits determine the accuracy level of

the reading. 11 is most accurate (2 periods used) and 10 is

the least accurate (1 period used). If less than 1 period

occurred during the measurement cycle, the lower two bits

are set to 10.

In smart fan tach mode, the TACH_EDGE field is honored in

the LM93 Status/Control register. If only one edge type is

active, the measurement always uses that edge type (rising

or falling). If both are active, the measurement uses which-

ever edge type occurs first.

Typically the minimum RPM captured by smart fan tach

mode is 900 RPM for a fan that produces two pulses per

revolution at about 50% duty cycle.

13.0 Inputs/Outputs

Besides all the pins associated with sensor inputs the LM93

has several pins that are assigned for other specific func-

tions.

13.1 ALERT OUTPUT

The ALERT output is an active-low open drain output signal.

The ALERT output is used to signal a micro-controller that

one or more sensors have crossed their corresponding limit

thresholds. This is generally not a fatal event unless the

micro-controller decides it to be.

If enabled, the ALERT output is asserted whenever any bit in

any BMC Error Status register is set (with the exception of

the fixed PROCHOT threshold bits). By definition, when

ALERT is enabled, it always matches the inverse of the

BMC_ERR bit in the LM93 Status/Control register. When the

ALERT output is disabled, an alert event can still be deter-

mined by reading the state of the BMC_ERR bit.

The ALERT functions like an interrupt. The LM93 does not

support the SMBus ARA (Alert Response Address) protocol.

ALERT is only de-asserted when there are no error status

bits set in any BMC Error Status registers. Alternatively,

software can disable the ALERT output to cause it to de-

assert. The ALERT output re-asserts once enabled if any

BMC Error Status register bits are still set.

Further information on how the ALERT output behaves can

be found in Section 15.7 MASKING, ERROR STATUS AND

ALERT.

13.2 RESET INPUT/OUTPUT

This pin acts as an active low reset output when power is

applied to the LM93. It is asserted when the LM93 first sees

a voltage that exceeds the internal POR level on its +3.3V

S/B V

DD input. The internal registers of the LM93 are reset to

their defaults when power is applied.

After this reset has completed, the RESET pin becomes an

input. When an external device asserts RESET, the LM93

clears the LOCK bit in the LM93 Configuration register. This

feature allows critical registers to be locked and provides a

controlled mechanism to unlock them.

Asserting RESET externally causes the Sleep State Control

error events to be masked according to the S4/5 masking

definitions. Refer to the register descriptions for more infor-

mation.

13.3 PWM1 AND PWM2 OUTPUTS

The PWM outputs are used to control the speed of fans. The

output signal duty cycle can automatically be controlled by

the temperature of one or more temperature zones. It is also

influenced by various other inputs and registers. See Section

15.10 FAN CONTROL for further information on the behavior

of the PWM outputs.

13.4 SCSI_TERMx INPUTS

These inputs can be used to monitor the status of the

electronic fuse on each of the SCSI channels. In prior imple-

mentations the reference voltage out to the terminators was

measured. When LVDS SCSI was introduced this reference

voltage could take on multiple voltage levels depending on

the mode of the SCSI bus. Also when the SCSI terminators

were disabled, the V

REF voltage could not be guaranteed.

Monitoring individual terminators was also pin intensive. All

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