LM93 datasheet(88/92 Pages) NSC

88 / 92 page

AC Electrical Characteristics

The following limits apply for +3.0 V

DC to +3.6 VDC, unless otherwise noted. Bold face limits apply for TA =TJ =TMIN to

MAX of the operating range; all other limits TA =TJ = 25˚C unless otherwire noted.

Symbol

Parameter

Conditions

Typical

(Note 9)

Limits

(Note 10)

Units

(Limits)

FAN RPM-TO-DIGITAL CHARACTERISTICS

Counter Resolution

bits

Number of fan tach pulses count is

based on

pulses

Counter Frequency

22.5

kHz

Accuracy

±6

% (max)

PWM OUTPUT CHARACTERISTICS

Frequency Tolerances

±6

% (max)

Duty-Cycle Tolerance

±2

±6

% (max)

RESET INPUT/OUTPUT CHARACTERISTICS

Output Pulse Width

Upon Power Up

250

330

ms (min)

ms (max)

Minimum Input Pulse Width

µs (min)

Reset Output Fall Time

1.6V to 0.4V Logic Levels

µs (max)

SMBUS TIMING CHARACTERISTICS

SMBCLK

SMBCLK (Clock) Clock Frequency

100

kHz (min)

kHz (max)

BUF

SMBus Free Time between Stop and

Start Conditions

4.7

µs (min)

HD;STA

Hold time after (Repeated) Start

Condition. After this period, the first

clock is generated.

4.0

µs (min)

SU;STA

Repeated Start Condition Setup Time

4.7

µs (min)

SU;STO

Stop Condition Setup Time

4.0

µs (min)

SU;DAT

Data Input Setup Time to SMBCLK

High

250

ns (min)

HD;DAT

Data Output Hold Time after SMBCLK

Low

300

930

ns (min)

ns (max)

LOW

SMBCLK Low Period

4.7

µs (min)

µs (max)

HIGH

SMBCLK High Period

4.0

µs (min)

µs (max)

Rise Time

µs (max)

Fall Time

300

ns (max)

TIMEOUT

Timeout

SMBDAT or SMBCLK low

time required to

reset the Serial Bus

Interface to the Idle State

ms (min)

ms (max)

POR

Time in which a device must be

operational after power-on reset

DD > +2.8V

500

ms (max)

Capacitance Load on SMBCLK and

SMBDAT

400

pF (max)

LM93 Datasheet(PDF) 88 Page - National Semiconductor (TI)

LM93 Datasheet(HTML) 88 Page - National Semiconductor (TI)

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