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LM93 Datasheet(PDF) 84 Page - National Semiconductor (TI) |
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LM93 Datasheet(HTML) 84 Page - National Semiconductor (TI) |
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84 / 92 page  16.0 Registers (Continued) 16.10 OTHER MASK REGISTERS 16.10.1 Register ECh GPI Error Mask Register Address Read/ Write Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Value ECh R/W GPI Error Mask GPI7 _MSK GPI6 _MSK GPI5 _MSK GPI4 _MSK GPI3 _MSK GPI2 _MSK GPI1 _MSK GPI0 _MSK FFh Bit Name R/W Description 0 GPI0_MSK R/W When this bit is set, GPI0 error events are masked. 1 GPI1_MSK R/W When this bit is set, GPI1 error events are masked. 2 GPI2_MSK R/W When this bit is set, GPI2 error events are masked. 3 GPI3_MSK R/W When this bit is set, GPI3 error events are masked. 4 GPI4_MSK R/W When this bit is set, GPI4 error events are masked. 5 GPI5_MSK R/W When this bit is set, GPI5 error events are masked. 6 GPI6_MSK R/W When this bit is set, GPI6 error events are masked. 7 GPI7_MSK R/W When this bit is set, GPI7 error events are masked. These bits mask the corresponding bits in the B_ and H_GPI Error Status Registers. They do not effect the GPI State register. 16.10.2 Register EDh Miscellaneous Error Mask Register Address Read/ Write Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Value EDh R/W Miscellaneous Error Mask RES DVccp2 _MSK DVccp1 _MSK SCSI2 _MSK SCSI1 _MSK VRD2 _MSK VRD1 _MSK 3Fh Bit Name R/W Description 0 VRD1_MSK R/W When this bit is set, VRD1_HOT error events are masked. 1 VRD2_MSK R/W When this bit is set, VRD2_HOT error events are masked. 2 SCSI1_MSK R/W When this bit is set, SCSI_TERM1 error events are masked. 3 SCSI2_MSK R/W When this bit is set, SCSI_TERM2 error events are masked. 4 DVccp1_MSK R/W When this bit is set, dynamic Vccp limit error events for AD_IN7 (CPU1) are masked. 5 DVccp2_MSK R/W When this bit is set, dynamic Vccp limit error events for AD_IN8 (CPU2) are masked. 7:6 RES R Reserved www.national.com 84 |
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