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LM93 Datasheet(PDF) 63 Page - National Semiconductor (TI) |
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LM93 Datasheet(HTML) 63 Page - National Semiconductor (TI) |
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63 / 92 page ![]() 16.0 Registers (Continued) 16.8.2 Register BDh Special Function Control 2 (Smart Tach Mode Enable and Fan Control Temperature Resolution Control) Register Address Read/ Write Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Value BDh R/W Special Function Control 2 RES RES ZN34 _RS ZN12 _RS STE4 STE3 STE2 STE1 00h Bit Name R/W Description 0 STE1 R/W Enable Smart Tach for Tach 1 1 STE2 R/W Enable Smart Tach for Tach 2 2 STE3 R/W Enable Smart Tach for Tach 3 3 STE4 R/W Enable Smart Tach for Tach 4 4 ZN12_RS R/W When this bit is set, the auto fan control will use 0.5˚C of resolution for zones 1 and 2 5 ZN34_RS R/W When this bit is set, the auto fan control will use 0.5˚C of resolution for zones 3 and 4 6 RES R Reserved 7 RES R Reserved Application Note: Enabling Smart Tach mode is not supported while either PWM output is configured for 22.5 kHz. The behavior of the part is undefined if this configuration is programmed. Register E0h Special Function TACH to PWM Binding must be setup when Smart Tach modes are enabled. 16.8.3 Register BEh GPI/VID Level Control Register Address Read/ Write Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Value BEh R/W GPI/VID Level Control GPI7 _LVL GPI6 _LVL GPI5 _LVL GPI4 _LVL RES P2_VID _LVL P1_VID _LVL 00h Bit Name R/W Description 0 P1_VID_LVL R/W If set, P1_VIDx inputs use alternate lower V IH and VIL levels 1 P2_VID_LVL R/W If set, P2_VIDx inputs use alternate lower V IH and VIL levels 3:2 RES R Reserved 4 GPI4_LVL R/W If set, GPIO4 input use alternate lower V IH and VIL levels 5 GPI5_LVL R/W If set, GPIO5 input use alternate lower V IH and VIL levels 6 GPI6_LVL R/W If set, GPIO6 input use alternate lower V IH and VIL levels 7 GPI7_LVL R/W If set, GPIO7 input use alternate lower V IH and VIL levels See the DC Electrical Characteristics for exact V IH and VIL levels. www.national.com 63 |
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