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LM93 Datasheet(PDF) 80 Page - National Semiconductor (TI) |
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LM93 Datasheet(HTML) 80 Page - National Semiconductor (TI) |
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80 / 92 page ![]() 16.0 Registers (Continued) 16.9 SLEEP STATE CONTROL AND MASK REGISTERS 16.9.1 Register E4h Sleep State Control Register Address Read/ Write Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Value E4h R Sleep State Control RES SB 07h Bit Name R/W Description 1:0 SB R/W Sleep State Control. Setting this field tells the LM93 which sleep state the system is in. Several error events are masked depending on the state of this field. 7:2 RES R Reserved SB Description 00 Sleep state = S0 Do not mask errors. 01 Sleep state = S1 Mask errors according to S1 mask registers and standard S1 masking. 10 Sleep state = S3 Mask errors according to S3 mask registers and standard S3 masking. 11 Sleep state = S4/5 Mask errors according to S4/5 mask registers and standard S4/5 masking. This mode is activated automatically if the RESET input is asserted. www.national.com 80 |
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