PC87591L datasheet(202/437 Pages) NSC

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Revision 1.07

4.13.7 ACB Clock Frequency Configuration

The ACB module enables the user to set the ACCESS.bus clock frequency. The SCLn clock period is set by SCLFRQ in

ACBnCTL2 and ACBnCTL3 registers. This clock low period may be extended by stall periods initiated by the ACB module

or by another ACCESS.bus device. In case of a conflict with another bus master, a shorter clock high period may be forced

by the other bus master until the conflict is resolved.

4.13.8 ACB Registers

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

ACB Register Map

ACB Serial Data Register (ACBnSDA)

The ACBnSDA register is a shift register used to transmit and receive data. The most significant bit is transmitted (received)

first and the least significant bit is transmitted (received) last. Reading or writing to the ACBnSDA register is allowed only

when SDAST in ACBnST register is set or for repeated starts after setting the START bit. An attempt to access the register

in other cases may produce unpredictable results.

Locations: Channel - 1 00 FF6016

Channel - 2 00 FFE016

Type: R/W

Mnemonic

Type

ACBnSDA

ACB Serial Data

R/W

ACBnST

ACB Status

Varies per bit

ACBnCST

ACB Control Status

Varies per bit

ACBnCTL1

ACB Control 1

R/W

ACBnADDR

ACB Own Address

R/W

ACBnADDR2

ACB Own Address 2

R/W

ACBnCTL2

ACB Control 2

R/W

ACBnCTL3

ACB Control 3

R/W

Bit

76543210

Name

Data

Bit

Description

7-0

Data.

PC87591L Datasheet(PDF) 202 Page - National Semiconductor (TI)

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