PC87591L datasheet(223/437 Pages) NSC

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Embedded Controller Modules (Continued)

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A write to an address within a Main Block section results in an erase of the Main Block section. A write to an ad-

dress within an Information Block section results in an erase of the Information Block section and its corresponding

Main Block section (e.g., Main Block section 0 and Information Block section 0).

●

Special Erase State

The Special Erase state is entered by a command from JTAG. Special erase enables erasing the entire ﬂash, ex-

cept for the factory parameters. It is the only operation on the ﬂash enabled for the JTAG when the ﬂash protection

ﬁeld is set to Protect. While in this state, the busy indicator is set. When the erase operation is completed, the data

is veriﬁed and the error bits are updated accordingly. During Special Erase state, reset is ignored. The protected

data information is always the last to be erased.

Both program and erase can be initiated by the host, core or JTAG interface. Note that no instruction fetch or data read/write

can be performed from/to the on-chip flash while it is being programed or erased.

While the JTAG Flash interface is enabled, the Debugger interface generates a reset, which causes the core, the Host in-

terface circuit and the core bus to be held in reset.

Flash Operation Timing Control

The Information Block read, the program and erase timings are controlled by internal timers. (The read timing from the Main

Block is controlled by the BIU configuration). The timers default on Power-Up reset to operate at a core frequency of 4 MHz.

Software may change this for operation with other core clock frequencies.

Section 4.16.7 on page 228 lists the timing control registers. Table 33 provides the values that should be programed into

the control registers for each core domain clock frequency. It is the responsibility of the firmware to make sure that the timing

control registers are set according to the current core domain clock frequency before any flash erase or flash program is

allowed.

Reset

While the on-chip flash is in Read state, driving reset aborts the current operation. Flash program and Erase operations con-

tinue to completion and the reset is extended accordingly. If reset is applied during Program or Erase state, the contents of

memory are not guaranteed (i.e., the program or erase may fail).

After reset, the on-chip flash defaults to Standby state.

When JTAG access to flash is disabled, the Flash interface is reset by all reset events. When the JTAG access to flash is

enabled, the PC87591x is reset, but the Flash interface allows flash access after all of the following have occurred:

●

The core clocks are stable in their default setting.

●

The protection information has been read.

●

Default values have been loaded into the Flash Interface registers.

On exiting from “JTAG Access to Flash” mode, the Flash Interface module is reset again (i.e., protection information is read

and default values loaded into the Flash Interface registers)

Table 33. Control Registers Values per Core Domain Clock

Core Domain

Clock

FLPSLR FLSTART FLTRAN FLPROG FLPERASE

FLSERASE

FLEND FLSEND FLRCV

[MHz]

[hex]

PC87591L Datasheet(PDF) 223 Page - National Semiconductor (TI)

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