PC87591L datasheet(352/437 Pages) NSC

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6.0 Host-Controlled Modules and Host Interface (Continued)

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352

Revision 1.07

Shared Memory Base Address Low Byte Register

This register describes the low byte for the user-defined memory zone mapped to the shared memory (decoded as bits 23

to 16 of the 32-bit address range, bits 15-0 are 0). This register is reset to 0016 on Host Domain Hardware reset.

Location: Index F616

Type: R/W

Shared Memory Size Conﬁguration Register

This register defines the size of the user-defined memory zone mapped to the shared memory. This register is reset to 0016

on host domain hardware reset.

Location: Index F716

Type: R/W

Bit

76543210

Name

User-Deﬁned Memory Zone Address Low

Reset

00000000

Bit

Description

7-0

User-Deﬁned Memory Zone Address Low. Deﬁnes the lower eight bits of the user-deﬁned memory block base

address. The base address should be aligned on the selected block size.

Bit

76543210

Name

Reserved

User-Defined Memory Zone Size

Reset

00000000

Bit

Description

3-0

User-Deﬁned Memory Zone Size. Deﬁnes the size, in bytes, of the zone window. The size is deﬁned as an

exponent of two, using the equation: NumOfBytes = 2n (where, n = User-Deﬁned Memory Zone size+16). The

zone must always be aligned to the window size (i.e., for a 128 Kbyte window, the 17 LSBs of the address

should be zero).

Bits

3 2 1 0 Size (Bytes)

0 0 0 0 64K (default)

. . .

0 1 0 1 2M

Other

Reserved

7-4

Reserved.

PC87591L Datasheet(PDF) 352 Page - National Semiconductor (TI)

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