PC87591L datasheet(350/437 Pages) NSC

350 / 437 page

6.0 Host-Controlled Modules and Host Interface (Continued)

www.national.com

350

Revision 1.07

Memory Range Programing

LPC memory transactions and/or LPC-FWH transactions can be forwarded to the PC87591x shared memory. The Shared

Memory Configuration register defines the transaction type and address range to which the PC87591x responds. The SHBM

strap inputs affect the default settings of the Shared Memory Configuration register to enable boot process from shared

memories. Two memory areas may be individually enabled: a user-defined zone and BIOS memory (either BIOS-LPC

and/or BIOS-FWH spaces).

To enable BIOS support, set the SHBM strap inputs to select any of the BIOS modes (see Section 2.3 on page 53 for de-

tails). The PC87591x responds to LPC memory read and write transactions to/from the BIOS address spaces, shown in

Table 60, as long as BIOS LPC Enable (bit 0) of the Shared Memory Configuration register is set.

Table 60. BIOS-LPC Memory Space Deﬁnition

The PC87591x responds to LPC-FWH read and write transactions to/from the high memory address range (’386’ mode

BIOS range), shown in Table 60, as long as BIOS FWH Enable (bit 3) of the Shared Memory Configuration register is set.

Table 61. BIOS-FWH Memory Space Deﬁnition

On host domain hardware reset in BIOS mode, the BIOS LPC Enable bit is set and the BIOS FWH Enable bit is set. The

PC87591x automatically detects the type of host boot protocol in use, via the first completed BIOS read operation after host

domain hardware reset. If the first read is an LPC memory read, the BIOS FWH Enable bit is cleared. If the first read is an

LPC-FWH read, the BIOS LPC Enable bit is cleared. Any other LPC or LPC-FWH transactions are ignored. The bits are

cleared only by the first read operation, allowing software to enable responding to these address ranges by setting the bit.

Figure 112 illustrates this behavior.

Figure 112. BIOS Mapping Enable Scheme

The user-defined shared memory enables sharing the memory without using it as a shared BIOS memory. The memory base

address in the host address space and the size of the shared memory are defined in the Shared Memory Base and Shared

Memory Size registers. Address bits above the block size are ignored and are internally replaced with 1s for the purpose of

address translation (e.g., for a 2 Mbyte block size, A21 through A31 are replaced with 1s).

Memory Address Range

Description

000E 000016 - 000E FFFF16

Extended BIOS range (Legacy); only when Extended

BIOS Enable bit in Shared Memory Range Configuration

000F 000016 - 000F FFFF16

BIOS Range (Legacy)

FFE0 000016 - FFFF FFFF16

386 mode BIOS range; this is the upper 2 Mbytes of the

memory space.

Memory Address Range

Description

FFE0 000016 - FFFF FFFF16

386 mode BIOS range; this is the upper 2 Mbytes of the

memory space. The PC87591x uses the first 21 address

lines and ID field to identify FWH access to the shared

memory.

Note: Only hardware-controlled transitions are shown;

other transitions are possible via software writes to the bits.

BIOS FWH Enable = 1

BIOS LPC Enable = 1

BIOS FWH Enable = 1

BIOS LPC Enable = 0

BIOS FWH Enable = 0

BIOS LPC Enable = 1

BIOS FWH Enable = 0

BIOS LPC Enable = 0

First LPC FWH Read

Host Domain

[SHBM = 0] Shared Disable BIOS

[SHBM

= 1] Enable

BIOS

First LPC Memory Read

Hardware Reset

PC87591L Datasheet(PDF) 350 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 350 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL