PC87591L datasheet(346/437 Pages) NSC

346 / 437 page

6.0 Host-Controlled Modules and Host Interface (Continued)

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346

Revision 1.07

SuperI/O Revision ID Register (SRID)

This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). The

Chip Rev is incremented on each revision.

Location: Index 2716

Type: RO

SuperI/O Conﬁguration 8 Register (SIOCF8)

Location: Index 2816

Type: R/W

RTC Disabled.

0: Enabled (default)

1: Disabled

6-5

General-Purpose Scratch.

SIOCF6 Software Lock. When set to 1 by software, it and other bits in this register can be cleared only by Host

Domain Hardware reset.

0: Write access to bits 0-6 of this register enabled (default)

1: Bits 6-0 of this register are read only.

Bit

76543210

Name

Chip ID

Chip Rev

Reset

See values in ﬁeld description

XXXXX

Bit

Description

4-0

Chip Rev. Identiﬁes the device revision.

7-5

Chip ID. Identiﬁes a speciﬁc device of the PC87591x family.

Bits

7 6 5

Device

0 0 0:

PC87591E

0 0 1:

PC87591S

1 0 0:

PC87591 L

Other:

Reserved

Bit

43210

Name

Reserved

Reset

00000

Bit

Description

7-0

Reserved.

Bit

Description

PC87591L Datasheet(PDF) 346 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 346 Page - National Semiconductor (TI)

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