PC87591L datasheet(342/437 Pages) NSC

342 / 437 page

6.0 Host-Controlled Modules and Host Interface (Continued)

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342

Revision 1.07

SuperI/O configuration section for the shared memory bridge. The number of address bits used for this decoding varies ac-

cording to the specified zones and their sizes. See “Memory Range Programing” on page 350 and “Shared Memory Config-

uration Register” on page 351 for details about the address range specifications.

6.1.5

Interrupt Serializer

The Interrupt Serializer translates internal IRQ sources into serial interrupt request data transmitted over the SERIRQ bus.

Figure 111 shows the interrupt serialization mechanism.

Figure 111. Interrupt Serialization Mechanism

The internal IRQ signals are fed into an IRQ Mapping and Polarity Control block. This block maps them to their associated

IRQ slots. The IRQs are then fed into the Interrupt Serializer, where they are translated into serial data and transmitted over

the SERIRQ bus.

6.1.6

Protection

The PC87591x provides features to protect the Personal Computer (PC) at software levels. The PC can be locked to protect

configuration bits and to prevent alteration of the device hardware configuration and several types of configuration settings.

The use of all protection mechanisms is optional.

6.1.7

LPC Interface

LPC Transactions Supported

The PC87591x LPC interface responds to the following LPC transactions as part of the standard Host Bus interface:

— I/O read cycles

— I/O write cycles

In addition, the Shared Memory module uses the following transactions:

— 8-bit memory read and write

— 8-bit FWH read and write

LPC transactions conform with Intel’s LPC Interface Specification, Revision 1.0.

The LPC- FWH read and write protocols are similar to memory read and write cycles. The specifications of these cycles are

listed below. The Address, Data, TAR and SYNC cycles are as specified for LPC memory read and write cycles. The START

and ID fields are similar to the equivalent cycle in LPC memory read and write transactions but differ in the data placed on

the LAD signals (see details in the cycle description).

Note: The PC87591x supports FWH transactions from LPC controllers that accept wait-sync and long wait-sync cycles. With

other LPC controllers, use the indirect write mechanism in the Shared Memory module to perform write operations.

FWH Read Cycle

1. START: 110116 (0xD).

2. ID field: FWH ID nibble (compared with bits 7-4 of shared memory; see “Shared Memory Configuration Register” on

page 351).

3. Address: Eight address nibbles, MS nibble first; see usage below).

4. TAR (two cycles).

5. SYNC.

6. DATA: Two data nibbles, LS nibble first (D3-D0, D7-D4).

7. TAR (two cycles).

IRQ Mapping,

Enable and Polarity

Control

Internal

IRQ

Sources

Control

Signals

Interrupt

Serializer

LPC Interface

SERIRQ

IRQ1

IRQ15

PC87591L Datasheet(PDF) 342 Page - National Semiconductor (TI)

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