PC87591L datasheet(343/437 Pages) NSC

343 / 437 page

6.0 Host-Controlled Modules and Host Interface (Continued)

Revision 1.07

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FWH Write Cycle:

1. START: 111016 (0xE).

2. ID field: FWH ID nibble (compared with bits 7-4 of shared memory; see “Shared Memory Configuration Register” on

page 351).

3. Address: Eight address nibbles MS nibble first (see usage below).

4. DATA: Two data nibbles, LS nibble first (D3-D0, D7-D4).

5. TAR (two cycles).

6. SYNC.

7. TAR (two cycles).

The ID field is compared with bits 7-4 of shared memory; see “Shared Memory Configuration Register” on page 351. If the

two match, the PC87591x continues handling the transaction; if they do not match, the current LPC-FWH transaction is ig-

nored.

LPC-FWH Address translation: The address field in the LPC-FWH transaction is constructed of eight nibbles. The first seven

correspond to the first LS seven address nibbles (A27-A0) as follows: The first nibble that appears corresponds to addresses

A27-A24, the second to A23-A20, until the seventh incoming nibble, which corresponds to addresses A3-A0. Incoming nib-

ble number eight is ignored. The MS bits of the 32-bit addresses are ‘1111’ (A31 - A28).

Core Interrupt

Whenever there is an LPC or FWH transaction that is responded to by any of the PC87591x logical devices, a positive pulse

is generated on the Host Access Wake-Up input of the MIWU module. This interrupt may be used to wake up the core for

handling any host activity.

CLKRUN Functionality

The PC87591x supports the CLKRUN I/O signal, the use of which is highly recommended in portable systems. This signal

is implemented according to the specification in PCI Mobile Design Guide, Revision 1.1, December 18, 1998. The PC87591x

supports operation with both a slow and stopped clock in ACPI state S0 (the system is active but is not being accessed).

The PC87591x drives the CLKRUN low to force the LPC bus clock into full speed operation when an IRQ is pending inter-

nally and waiting to be sent through the serial IRQ.

LPCPD Functionality

The PC87591x supports the LPCPD input. This signal is used when the VDD chip supply is not shared by all residents of the

LPC bus. The LPCPD signal conforms with Intel’s LPC Interface Specification, Revision 1.0. Note that if the PC87591x pow-

er supply exists while LPCPD is active, it is not mandatory to reset the PC87591x when LPCPD is de-asserted.

6.1.8

SuperI/O Configuration Registers

This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of

2016 - 2E16). See Table 55 for a summary and directory of these registers.

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

Table 55. SuperI/O Conﬁguration Registers

Index

Mnemonic

Power Well

Type

2016

SID

SuperI/O ID

VDD

2116

SIOCF1

SuperI/O Conﬁguration 1

VDD

Varies per bit

2216 -2416 Reserved exclusively for National use

2516

SIOCF5

SuperI/O Conﬁguration 5

VDD

R/W

2616

SIOCF6

SuperI/O Conﬁguration 6

VDD

R/W

2716

SRID

SuperI/O Revision ID

VDD

2816

SIOCF8

SuperI/O Conﬁguration 8

VDD

R/W

2916

SIOCF9

SuperI/O Conﬁguration 9

VDD

R/W

PC87591L Datasheet(PDF) 343 Page - National Semiconductor (TI)

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