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PC87591L Datasheet(PDF) 344 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 344 Page - National Semiconductor (TI) |
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344 / 437 page  6.0 Host-Controlled Modules and Host Interface (Continued) www.national.com 344 Revision 1.07 SuperI/O ID Register (SID) This register contains the identity number of the chip. The PC87591x is identified by the value EC16. Location: Index 2016 Type: RO SuperI/O Configuration 1 Register (SIOCF1) Location: Index 2116 Type: Varies per bit 2A16 -2C16 Reserved exclusively for National use 2D16 SIOCFD SuperI/O Configuration D VPP R/W 2E16 Reserved exclusively for National use Bit 76543210 Name Family ID Reset EC16 Bit Description 7-0 Family ID. These bits identify a family of devices with similar functionality but with different options implemented. Bit 76543210 Name Reserved Number of DMA Wait States Number of I/O Wait States Software Reset SuperI/O Devices Enable Reset 00010001 Bit Type Description 0 R/W SuperI/O Devices Enable. Controls the function enable of all the PC87591x SuperI/O logical devices, except shared memory and Mobile System Wake-Up Control (MSWC). This bit enables the simultaneous disabling of these modules using a write to a single bit. 0: All SuperI/O logical devices in the PC87591x are disabled, except MSWC and shared memory 1: Each SuperI/O logical device is enabled according to its Activate register (Index 3016) (default) 1WO Software Reset. Read always returns 0. 0: Ignored (default) 1: Triggers the Host Domain Software Reset event, which resets the logical devices (see Section 6.1.3 on page 341) 3-2 R/W Number of I/O Wait States. Bits 3 2 Number 0 0: 0 (default) 0 1: 2 1 0: 6 1 1: 12 Table 55. SuperI/O Configuration Registers (Continued) Index Mnemonic Register Name Power Well Type |
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