PC87591L datasheet(367/437 Pages) NSC

367 / 437 page

Host-Controlled Modules and Host Interface (Continued)

Revision 1.07

367

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Year Register (YER)

Location: Index FF16

Type: R/W

RTC Control Register A (CRA)

This register controls test selection, among other functions and cannot be written before reading bit 7 of the CRD register.

Location: Index 0A16

Type: R/W

Table 66. Divider Chain Control and Test Selection

Bit

76543210

Name

Year Data

Reset

00000000

Bit

Description

7-0

Year Data. Values may be 00 to 99 in BCD format or 00 to 63 in binary format.

Bit

76543210

Name

Update in

Progress

Divider Chain Control 2-0

Periodic Interrupt Rate Select 3-0

Reset

00100000

Bit

Description

3-0

Periodic Interrupt Rate Select. These R/W bits select one of 15 output taps from the clock divider chain to

control the rate of the periodic interrupt (see Table 67 on page 368 and Figure 115 on page 358). They are

cleared to 0002 as long as bit 7 of CRD register is 0.

6-4

Divider Chain Control. These R/W bits control the conﬁguration of the divider chain for timing generation and

Update in Progress. This RO bit is not affected by reset; it is 0 when bit 7 of CRB register is 1.

0: Timing registers not updated within 244

µs

1: Timing registers updated within 244

µs

DV2

DV1

DV0

Conﬁguration

CRA6

CRA5

CRA4

Oscillator Disabled

Normal Operation

011

Test

Divider Chain Reset

PC87591L Datasheet(PDF) 367 Page - National Semiconductor (TI)

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