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PC87591L Datasheet(PDF) 388 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 388 Page - National Semiconductor (TI) |
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388 / 437 page ![]() 7.0 Device Specifications (Continued) www.national.com 388 Revision 1.07 7.6.4 BIU Timing Symbol Figure Description Reference Conditions Min Max Unit BIU Input Timing t1 134, 136 to 138 Input setup time D0-15 Before RE CLK 15 ns t2 134, 136 to 138 Input hold time D0-15 After RE CLK 0 ns BIU Output Timing t3 134 to 139 Output valid time A0-17, BE0,1CBRD, D0-15 After RE CLK 14 ns t4 134 to 139 Output valid time BST0-2 After RE CLK 0.5 * tCLK +14ns - t5 134 to 138 Output active/inactive time RD, SEL0-1, SELIO After RE CLK 14 ns t6 134, 135 Output active/inactive time WR0-1 After RE CLK 0.5 * tCLK +14ns - t7 136 Minimum inactive time RD After RE RD tCLK − 5ns - t8 134, 135 Output float time A0-17, D0-15,RD, SEL0- 1,SELIO,WR0-1 After RE CLK 14 ns t9 134, 135 Minimum delay time From RE RD to D0-15 drive tCLK − 8ns - t10 135 Minimum delay time From RE RD to RE SELn 0 ns t11 135 Minimum delay time From RE SELx to FE SELy0 ns t12 134 to 139 Output hold time A0-17, BE0-1, CBRD, D0- 15, RD, SEL0-1, SELIO After RE CLK 0 ns t13 134 to 139 Output hold time BST0-2,WR0-1 After RE CLK 0.5 * tCLK − 4ns - t14 135 D0-15 valid in late write bus cycles Before RE WR0-1 (K + 0.5) * tCLK − 8ns - |
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