PC87591L datasheet(385/437 Pages) NSC

385 / 437 page

7.0 Device Specifications (Continued)

Revision 1.07

385

www.national.com

7.6.3

Clock Timing

Symbol

Figure

Description

Reference Conditions

Min

Max

Unit

Clock Input Timing

t32KCLKIN

131

Required clock period for

32KCLKIN

From RE to RE of 32KCLKIN

t32NOM = 30.517578

30.5145

(t32NOM −

100ppm)

30.5206

(t32NOM +

100ppm)

µs

Clock Output Timing

tCLK

132

CLK period

At 2.0V (both edges)

250

tCLKh

132

CLK high time

At 2.0V (both edges)

0.5 * tCLK −

5ns

tCLKl

132

CLK low time

At 0.8V (both edges)

0.5 * tCLK −

5ns

tCLKr

132

CLK rise time

0.8V to 2.0V

tCLKf

132

CLK fall time

2.0V to 0.8V

tCLKw

133

CLK wake-up time

From wake-up event until

CLK starts toggling

100

µs

tCLKINTst

133

tCLK period

Active mode in steady state

0.99 *

tCLKINTnom

1. tCLKINTnom is deﬁned in Table 36 on page 241.

1.01 *

tCLKINTnom

tCLKINTwk

133

tCLK period

After wake-up from Idle

0.9 *

tCLKINTnom

1.1 *

tCLKINTnom

tCLKstab

133

tCLK stabilization time

After wake-up from Idle

0.5

t32KW

131

32K oscillator wake-up time After VBAT >VLOWBAT

t32KD

132

CLK delay time

After VCC >VCCON

Flash Operation Frequency

fFMAX

Flash Section 0 and 1

maximal operation frequency

in Fast Read

CLK period

MHz

tFLPMAX

Flash Section 0 and 1

maximal operation frequency

in Low Power

CLK period

TBD

MHz

PC87591L Datasheet(PDF) 385 Page - National Semiconductor (TI)

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