ML7396AB datasheet(66/140 Pages) LAPIS

66 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

66/140

Clearing interrupt condition

The following table shows the condition of clearing each interrupt.

Interrupt notification

Requirements for clearing interrupt

INT[0]

CLK stabilization completion

After the interrupt generation

INT[1]

Reserved

INT[2]

VCO calibration completion

After the interrupt generation

INT[3]

Packet discard completion during

Address Filtering function

After the interrupt generation

INT[4]

FIFO-Empty detection

After the interrupt generation

(must clear before the next FIFO-Empty trigger timing)

INT[5]

FIFO-Full detection

After the interrupt generation

(must clear before the next FIFO-Full trigger timing)

INT[6]

INT[7]

INT[8]

CCA completion

After the interrupt generation

(must clear before the next CCA execution)

* clearing interrupt erases CCA result as well

INT[9]

Diversity search completion

After RX completion interrupt(INT[18/19]), must cleare

with RX completion interrupt

* during RECEIVE stare, clearing is prohibited.

INT[10]

RF state transition completion

After the interrupt generation

INT[11]

SFD detection

After the interrupt generation

INT[12]

RX length error

After the interrupt generation

INT[13]

TX length error

After the interrupt generation

INT[14]

RX FIFO access error

After the interrupt generation

INT[15]

TX FIFO access error

After the interrupt generation

(must clear before the next packet transmission)

INT[16/17]

FIFO0/FIFO1 TX completion

After the interrupt generation

(must clear before the next packet transmission)

INT[18/19]

FIFO0/FIFO1 RX completion

After the interrupt generation

(must clear before the next packet reception)

INT[20/21]

FIFO0/FIFO1CRC error detection

After the interrupt generation

* clearing interrupt erases CRC result (CRC_RSLT1/0).

INT[22/23]

FIFO0/FIFO1 TX data request

accept completed

After TX completion interrupt (INT[16/17])

(must clear before the next packet transmission)

* during TRANSMIT state, clearing is prohibited.

INT[24]

AutoAck ready

After the interrupt generation

INT[25]

PLL unlock detection

After the interrupt generation

(must clear before the next packet transmission or

reception)

ML7396AB Datasheet(PDF) 66 Page - LAPIS Semiconductor Co., Ltd.

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