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ML7396AB Datasheet(PDF) 17 Page - LAPIS Semiconductor Co., Ltd. |
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ML7396AB Datasheet(HTML) 17 Page - LAPIS Semiconductor Co., Ltd. |
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17 / 140 page  FEDL7396A/B/E-07 ML7396A/B/E 17/140 ●Clock output characteristics Clock output can be controled by [CLK_SET:B0 0x02] register (Initial value:enable), Clock output from DMON pin. Item Symbol Condition Min Typ Max Unit Clock output frequency FCLKOUT - 0.0088 6 36 MHz 12MHz 30 - 70 % Load capacitance CL=20pF Clock output duty ratio DCLKOUT (*1) Other than above 48 50 52 % *1 Duty ratio will be H:L = 1:2 when output frequency is 12MHz.. Refer [CLK_OUT: B0 0x03] register (). FCLKOUT DMON ●Reset Item Symbol Condition Min Typ Max Unit All power supply pins RESETN delay time (Power on) TRDL 1.5 - - ms (After power on) RESETN pulse period TRPW 200 - - ns (When starting from VDDIO=0V) RESETN pulse period 2 (*1) TRPW2 1.5 - - ms VDD>1.8V (When starting from VDDIO ≠0V) RESETN rising period TRRST - - 1 ms VDD level GND level VDDIO TRPW TRPW2 RESETN TRDL TRRST (*1) When starting from VDDIO≠.0V, input a pulse to the RESETN signal after VDDIO exceeds 1.8V. |
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