ML7396AB datasheet(31/140 Pages) LAPIS

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FEDL7396A/B/E-07

ML7396A/B/E

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FIFO control method when using FIFO address

(1) TX

Condition: AUTO_TX ([PACKET_MODE_SET:B0 0x45(2)]) =0b1 and FIFO access size is 128 bytes.

Set

[FAST_TX_SET;B0 0x6A] register and FIFO_ADR_EN ([PACKET_MODE_SET:B0 0x45(7)]) =0b1.

Write256 bytesdata to FIFO ([WR_TX_FIFO:B0 0x7E] register) via SPI interface.

* When the amount of written data reaches [FIFO_TX_SET:B0 0x6A] register, transmission starts.

Read

[RD_FIFO_LAST:B0 0x7C] register. When FIFO address indication (hereafter, Read pointer) is 128 or more and the

remaining TX data is 128 bytes or more, writing 128 bytes data to FIFO. If remaining TX data is less than 128 bytes, go

Read [RD_FIFO_LAST] register. When Read pointer is 64 or less and the remaining Tx data is 128 bytes or more,

writing 128 bytes data to FIFO. If remaining TX data is less than 128 bytes, go to

Repeat

and

until for the necessary amount of TX data.

Writing whole remaining data to FIFO and wait TX completion interrupt (INT[16] / INT[17], group3) notification.

Yes

Read pointer

≥128?

[RD_FIFO_LAST:B0 0x7C]

Yes

Remaining Tx data

≥128 bytes?

Write 128 bytes data

to a FIFO

[WR_TX_FIFO:B0 0x7E]

Yes

≥Read pointer?

[RD_FIFO_LAST:B0 0x7C]

Remaining Tx data

≥128 bytes?

Wait for TX completion int.

[INT_SOURCE_GRP3:B0 0x26]

Write 256 bytes

to a FIFO

[WR_TX_FIFO:B0 0x7E]

Yes

Time

Total Tx data

[Transmit]

Start transmission

TX FIFO address indication

255

TX FIFO address indication (read pointer)

increments after Tx start.

After transimitting 256

byte data, the

address indication is turned to 0 and

increments again.

Write 128 bytes data

to a FIFO

[WR_TX_FIFO:B0 0x7E]

Write remaining data

to a FIFO

[WR_TX_FIFO:B0 0x7E]

If data amount written to a FIFO exceeds

the FAST_TX_TRG[7:0], TX will start.

ML7396AB Datasheet(PDF) 31 Page - LAPIS Semiconductor Co., Ltd.

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