ML7396AB datasheet(50/140 Pages) LAPIS

50 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

50/140

The follwing is timing chart for CCA determination exclusion under strong signal.

[During IDLE_WAIT counting, detected extremly strong signal. After the given signal is out of averaging target, IDLE

detection case]

[Condition]

CCA normal mode

ADC_CK_SEL ([ADC_CLK_SET: B0 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0] ([ED_CTRL: B0 0x1B(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0] ([IDLE_WAIT_L/H: B0 0x17/18(1-0)])=0b00_0000_0111(IDLE detection period 112μs)

ED VALUE>CCA_IGNORE_LEVEL

[Note]

1. After issuing CCA command, transit into no-input state, and exit this state after filter stbilization.

2. When the iput level chnge from no-input to -80dBm, it takes around 32 μs for indicating -80dBm ED value.

ED7

INVALID

(0-7)

(1-8)

(6-13)

ED8

ED13

ED14

0x001

0x006

0b11 (on-going)

0x000

(14-21)

(7-14)

ED value>CCA_IGNORE_LEVEL

detection and reset

Due to extreme strong signal detection,

CCA_RSLT is not indicating IDLE.

CCA_RSLT[1:0]=0b11 do not generate interrupt

ED15

(8-15)

ED21

(22-29)

ED22

(15-22)

0x007

ED29

0b00 (IDLE)

Resume counting due to the extreme

strong signal is out of averaging target.

CCA _RSLT maintains until

IDLE/BUSY detected.

ED value<CCA_IGNORE_LEVEL

ED value <CCA_IGNORE_LEVEL

ED value

●●●

(internal signal)

Average ED value <CCA_TH_LV

(If average ED value >CCA_TH_LL, then BUSY detection.)

ED_Value[7:0]

●●●

[ED_RSLT: B0 0x16]

CCA_PROG[9:0]

●●●

[CCA_PROG_L/H:B0 0x19/1A]

CCA_RSLT[1:0]

0b10 (on-going)

[CCA_CNTRL: B0 0x15(1-0)]

CCA_DONE

[CCA_CNTRL: B0 0x15(2)]

ML7396AB Datasheet(PDF) 50 Page - LAPIS Semiconductor Co., Ltd.

ML7396AB Datasheet(HTML) 50 Page - LAPIS Semiconductor Co., Ltd.

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