ML7396AB datasheet(28/140 Pages) LAPIS

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FEDL7396A/B/E-07

ML7396A/B/E

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●FIFO

ML7396 family has on-chio two 256byte FIFOs as TX -RX buffer. However, one FIFO can store only one packet. (one packet

cannot use two FIFOs).

During RX, RX data is stored in a FIFO (byte by byte), and the host MCU wil read RX data through SPI. Duting TX, the host

MCU write TX data to a FIFO (byte by byte) through SPI and tenasmitting through RF.

Followings show the data format stored in FIFO.

As described below, input data format will be different according to the setting value to IEEE_MODE ([PACKET

MODE_SET:B0 0x45(1)]). (Regardless of IEEE_MODE, preamble and SFD bits are not stored into FIFOs)

[IEEE802.15.4g mode] (IEEE_MODE =0b1)

[Note; Length, CRC and ED value will be stored into data strage area other than FIFO.]

[IEEE802.15.4d mode] (IEEE_MODE =0b0)

Length

PSDU

(CRC)

2byte

2/4byte

[FEC/CRC_SET]

B0 0x46

2045/2043byte

LSB

MSB

(ED)

1byte

[PACKET_MODE_SET]

B0 0x45

(User data)

Length

(CRC)

1byte

128byte

125byte

LSB

MSB

(ED)

1byte

[PACKET_MODE_SET]

B0 0x45

Length (max: 127byte)

2byte

PSDU

(User data)

Data area stored into a FIFO

Length (max: 2047byte)

[Note; Length, CRC and ED value will be stored into data strage area other than FIFO.]

Writeing or reading FIFO will be done through SPI with burst access. TX data is written to [WR_TX_FIFO:B0 0x7E] register,

and RX data is read from [RD_RX_FIFO:B0 0x7F] register. Continuous access increments internal FIFO address

automatically. If burst access is suspended during write or read operation, address will be kept until the packet will beagain.

Two FIFOs (bank0, bank1) will be accessed one by another. If the host MCU writes TX data to a FIFO during RX, RX FIFO

will use only single FIFO. Control of switching FIFO banks will be done automatically. FIFO status can be checked by

[PD_DATA_REQ:B0 0x28] or [PD_DATA_IND:B0 0x29] register.

[Note]

When using IEEE802.15.4d mode, it is need to read “Length+1” bytes of data from RX FIFO for switching the FIFO

banks correctly. (The last byte is invalid data.)

In both TX and RX, Length indicates PSDU length including CRC field. (not including ED fieled if selected)

However during TX, the host MCU writes PSDU excluding CRC field to a FIFO. During RX, the host MCU should read

Lngth field, user data field and CRC fieled from a FIFO.

ML7396AB Datasheet(PDF) 28 Page - LAPIS Semiconductor Co., Ltd.

ML7396AB Datasheet(HTML) 28 Page - LAPIS Semiconductor Co., Ltd.

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