ML7396AB datasheet(88/140 Pages) LAPIS

88 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

88/140

■Flow Charts

●Initialization

In initialization status, interrupt process, registers setting, VCO calibration are necessary.

(1) Interrupt process

Upon reset, all interrupt notification settings ([INT_EN_GRP1-4:B0 0x2A-0x2D]) are enabled.

After hard reset is released, INT[00] (group 1: Clock stabilization completion interrupt) will be detected. After INT[00]

notification, please mask unused interruput elements by using [INT_EN_GRP1:B0 0x2A] to [INT_EN_GRP4] registers.

If interrupt elements are stored internnaly, interrupt will generate as soon as interrupt is unmasked, unless clearing the

interrpt. When clearing interrupt, it is recommended to clear interrput after masking the interrupt.

(2) Registers setting

In reset value setting, clock is output from DMON pin (#17). If clock output is not used, please assign another

monitoring function to DMON pin and terminate clock output.

After hard reset is released, all registers are accesible except for FIFO access registers and BANK1 registers before

INT[00] notification.

(3) VCO calibration

Executing VCO calibration after setting upper and lower limit of the operation frequency range. Operating frequency

should be in the calibration frequency range. In case of using frequency which is outside of calibration frequency range,

calibration process has to be performed again with proper frequency.

During VCO calibration, please register access is prohibited.

ML7396AB Datasheet(PDF) 88 Page - LAPIS Semiconductor Co., Ltd.