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ML7396AB Datasheet(PDF) 93 Page - LAPIS Semiconductor Co., Ltd. |
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ML7396AB Datasheet(HTML) 93 Page - LAPIS Semiconductor Co., Ltd. |
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93 / 140 page ![]() FEDL ML 7396A/B/E-07 7396A/B/E 93/140 ●RX mode (DIO mode) DIO (RX) mode can be selected by setting DIO_EN ([PLL_MON/DIO_SEL:B0 0x69(1)]) =0b1 and RX_FIFO_MON ([PLL_MON/DIO_SEL:B0 0x69(1)]) =0b1. In DIO (RX) mode, when issuing RX_ON command, preamble and SFD detection will be started. After preamble and SFD are detected, RX data is output through DIO pin (#15). RX Data following SFD field are output and RX data should be read at rising edge of DCLK from DCLK pin (#16). After RX completion, TRX_OFF commnand should be issued. Like packet mode, preamble and SFD detection are done according to the settings of [PREAMBLE_SET:B0 0x39], [SFD1_SET1:B0 0x3A] to [SFD1_SET4:B0 0x3D], [RX_PR_LEN/SFD_LEN:B0 0x43] and [SYNC_CONDITION:B0 0x44] registers.After SFD is deteceted, SFD detection interrupt (INT[11] group2) will generate. The first RX data is output at the first rising edge of DCLK after SFD detection interrupt notification.(Timing from SFD detection interrupt to the first DCLK rising edge is 9μs at 100kbps setting.) START Set DIO_EN =0b1 RX_FIFO_MON =0b1 [PLL_MON/DIO_SEL:B0 0x69(1,0)] Detect condition setting * Like packet mode, detect pattern should be set to ([PREAMBLE_SET:B0 0x39] and [SFD_SET1-4:B0 0x3A-3D] registers. [PREAMBLE_SET:B0 0x39] [SFD1_SET1-4:B0 0x3A-3D] [RX_PR_LEN/SFD_LEN:B0 0x43] [SYNC_CONDITION:B0 0x44] Note: Different from DIO (TX) mode setting. RX_ON issue [RF_STATUS:B0 0x6C] END No Yes Yes No DCLK output? * Afetr entering RX_ON state, DCLK will be output regardless of RX data. [DCLK pin (#16)] Read RX data * RX data should be read at rising edge of DCLK. [DIO pin (#15)] TX completion? TRX_OFF issue [RF_STATUS:B0 0x6C] |
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