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ML7396AB Datasheet(PDF) 19 Page - LAPIS Semiconductor Co., Ltd. |
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ML7396AB Datasheet(HTML) 19 Page - LAPIS Semiconductor Co., Ltd. |
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19 / 140 page  FEDL7396A/B/E-07 ML7396A/B/E 19/140 ■Registers ●Register map It is consist of 3bank, BANK0, BANK1, BANK2. Each BANK has address space of 0x00 to 0x7F, 128 byte in total. The space shown as gray highlighted part is not implemented in LSI or reserved bits. TX/RX FIFO is implemented in PHY block, those register except for FIFO is implemented in SPI block. The address not exist in the memory map is not accessible. Also, the address is not accessible during the VCO calibration. In each BANK, there are some registers that can not be access unless give access allowance by TST_ACEN ([BANK_SEL: B0/B1/B2 0x00(7)] =0b1. Such registers are marked with ”#” in the following list. The TST_ACEN enable setting is required in the initial setting or test mode setting, but it is recommended to set disable when in normal operation to avoid miss-setting. For registers whose setting value is specified by the “ML7396Family_InitialRegisterSetting” file, please set the value shown in the file. : Implemented as functionable register : Implemented as reserved bits |
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