ML7396AB datasheet(63/140 Pages) LAPIS

63 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

63/140

Interrupt generation timing

In each interrupt generation, timing from reference point to interrupt interrupt generation (nitification) are described in the

following table. Timeout procedure for interrupt notification waiting, are also described below.

[Note]

(1)The values are decribed in units of “symbol time” in the below table is the value at 100kbps. If using other data, please use

20, 5, and 2.5 for 50kbps, 200kbps, and 400kbps, respectively.

(2)Below table uses the following format of TX/RX data.

24 byte

(3)Even if each interrupt notification is masked, in case of interrupt occurrence, interrupt elements are stored internnaly.

Therefore, as soon as interrupt notification is unmasked, interrupt will generate.

Interrupt notification

Reference point

Time from reference point to interrupt generation

or interrupt generation timing

RESETN release

(upon power-on)

660μs

INT[0]

CLK stabilization

completion

SLEEP release

(recovered from

SLEEP)

660μs

INT[1]

INT[2]

VCO calibration

completion

VCO calibration

start

230μs

INT[3]

Packet discard

completion during

Address Filtering

function

SFD detection

(1)If ADDFIL_NG_SET([PACKET_MODE_SET:B0 0x45(5)])

=0b0, the right timing to address mismatch detection.

(2)If ADDFIL_NG_SET([PACKET_MODE_SET:B0 0x45(5)])

=0b1,

(When FEC is disabled)

28byte (Length to CRC) * 8bit * 10(symbol time) + process

delay(5.55μs) =2245.55μs

(When FEC is enabled)

28byte (Length to CRC) * 2 * 8bit *10(symbol time) + process

delay(315.55μs) =4795.55μs

(TX)

TX_ON command

(* 1)

Empty trigger level is set to 0x02

(When FEC is disabled)

37 byte (preamble to 23th data) * 8bit * 10 (symbol time)

=2960μs

(When FEC is enabled)

{12byte (preamble to SFD) + 25byte(Length to 23th data) * 2}

* 8bit* 10(symbol time) + RF wake-up & process delay (106μs)

=5066μs

INT[4]

FIFO-Empty detection

(RX)

By FIFO read, remaining FIFO data is under trigger level

(TX)

By FIDO write, FIFO usage exceeds trigger level

INT[5]

FIFO-Full detection

(RX)

SFD detection

Full trigger level is set to 0x05

(When FEC is disabled)

8byte (Length + 6

th data) * 8bit * 10(symbol time) =640μs

(Wwhen FEC is enabled)

8byte (Length + 6

th data) * 8bit * 2 * 10(symbol time) + process

delay(305μs) =1585μs

(INT[6])

(INT[7])

(* 1) Befor issuing TX_ON, writing full-length TX data into a FIFO.

2 byte

10 byte

2 byte

SFD

CRC

Length

Preamble

User data

ML7396AB Datasheet(PDF) 63 Page - LAPIS Semiconductor Co., Ltd.

ML7396AB Datasheet(HTML) 63 Page - LAPIS Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL