DS2155 datasheet(229/262 Pages) DALLAS

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DS2156

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Table 33-B. ID Code Structure

MSB

LSB

Version

Contact Factory

Device ID

JEDEC

4 bits

16 bits

00010100001

Table 33-C. Device ID Codes

PART

16-BIT ID

DS2156

0019h

DS2155

0010h

DS21354

0005h

DS21564

0003h

DS21352

0004h

DS21562

0002h

33.3 Test Registers

IEEE 1149.1 requires a minimum of two test registers, the boundary scan register and the bypass register.

An optional test register, the identification register, has been included with the DS2156 design. It is used

with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.

33.4 Boundary Scan Register

This register contains both a shift register path and a latched parallel output for all control cells and digital

I/O cells. It is n bits in length. See Table 33-D for cell bit locations and definitions.

33.5 Bypass Register

This is a single one-bit shift register used with the BYPASS, CLAMP, and HIGH-Z instructions that

provides a short path between JTDI and JTDO.

33.6 Identification Register

The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register

is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.

See Table 33-B and Table 33-C for more information on bit usage.

DS2155 Datasheet(PDF) 229 Page - Dallas Semiconductor