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SI3021 Datasheet(PDF) 46 Page - List of Unclassifed Manufacturers

Part # SI3021
Description  3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT
PDF  54 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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SI3021 Datasheet(HTML) 46 Page - List of Unclassifed Manufacturers

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Si 30 35
46
Rev. 1.2
Pin Descriptions: Si3021
Table 21. Si3021 Pin Descriptions
SOIC
Pin #
TSSOP
Pin #
Pin Name
Description
113
MCLK
Master Clock Input.
High speed master clock input. Generally supplied by the system crystal
clock or modem/DSP.
214
FSYNC
Frame Sync Output.
Data framing signal that is used to indicate the start and stop of a
communication/data frame.
315
SCLK
Serial Port Bit Clock Output.
Controls the serial data on SDO and latches the data on SDI.
416
VD
Digital Supply Voltage.
Provides the digital supply voltage to the Si3021, nominally either 5 V or
3.3 V.
51
SDO
Serial Port Data Output.
Serial communication data that is provided by the Si3021 to the modem/DSP.
62
SDI
Serial Port Data Input.
Serial communication and control data that is generated by the modem/DSP
and presented as an input to the Si3021.
7
3
FC/RGDT
Secondary Transfer Request Input/Ring Detect Output.
An optional signal to instruct the Si3021 that control data is being requested
in a secondary frame. When daisy chain is enabled, this pin becomes the
ring detect output. Produces an active low rectified version of the ring signal.
8
4
RESET
Reset Input.
An active low input that is used to reset all control registers to a defined, ini-
tialized state. Also used to bring the Si3034 out of sleep mode.
95
AOUT
Analog Speaker Output.
Provides an analog output signal for driving a call progress speaker.
1
2
3
4
5
6
7
8
9
10
11
12
13
16
15
14
MCLK
FSYNC
SCLK
VD
SDO
SDI
FC/RGDT
RESET
OFHK
RGDT/FSD
M0
VA
GND
C1A
M1
AOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
16
15
14
VD
SCLK
FSYNC
MCLK
OFHK
RGDT/FSD
M0
VA
SDO
SDI
FC/RGDT
RESET
AOUT
M1
C1A
GND
Si3021 (SOIC)
Si3021 (TSSOP)



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